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Instruction Set Architecture

Ajit Pal

ProfessorDepartment of Computer Science and Engineering

Indian Institute of Technology Kharagpur

INDIA-721302

Computer Architecture and Organization

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Outline

An Instruction

Instruction Set Architecture

Classification of ISAs

Classification of Operations

Operands

Instruction Format

Addressing Modes

Evolution of the Instruction Set

RISC Versus CISC

MIPS Instruction Set

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Aji t Pal, IIT Kharagpur

An Instruction

An instruction can be considered as a wordin

processors languageWhat information an Instruction should coveyto the CPU?

opcode Addr of OP1 Addr of OP2 Dest Addr Addr of next intr

The instruction is too long if everything specifiedexplicitly

More space in memory

Longer execution timeHow can you reduced the size of an instruction?

Specifying information implicitlyHow?

Using PC, ACC, GPRs, SP

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InstructionSet Architecture

Instruction Set Architecture is the structure of acomputer that a machine language programmer (or acompiler) must understand to write a correct (timingindependent) program for that machine.

The ISA defines:

Operations that the processor can executeData Transfer mechanisms + how to access dataControl Mechanisms (branch, jump, etc)Contract between programmer/compiler and HW

ISA is important:Not only from the programmers perspective.From processor design and implementationperspectives as well.

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InstructionSet Architecture

Programmer visible part of a processor:

Registers(where are data located?)

Addressing Modes(how is data accessed?)

Instruction Format(how are instructions

specified?)

Exceptional Conditions(what happens if

something goes wrong?)

Instruction Set(what operations can be

performed?)

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ISA Design Choices

Types of operations supported

e.g. arithmetic/logical, data transfer, control transfer,system, floating-point, decimal (BCD), string

Types of operands supportede.g. byte, character, digit, halfword, word (32-bits),

doubleword, floating-point number

Types of operand storage allowede.g. stack, accumulator, registers, memory

Implicit vs. explicit operands in instructions andnumber of eachOrthogonality of operands, operand location, andaddressing modes

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Determined by the means used for storing data in CPU:

The major choices are:

A stack, an accumulator,or a set of registers

Stack architecture:

Operands are implicitly on top of the stack Accumulator architecture:

One operand is in the accumulator (register) and the others are

elsewhere

Essentially this is a 1 register machine Found in older machines

General purpose registers: Operands are in registers or specific memory locations.

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Evolution of ISAs

Single Accumulator

(Manchester Mark I,IBM 700 series 1953)

General Purpose Register Machines

Complex Instruction Sets RISC

(Vax, Intel 386 1977-85)(MIPS, IBM RS6000, . . .1987)

Stack

(Burroughs, HP-3000 1960-70)

Accumulator Architectures (EDSAC, IBM-701)Special-purpose Register ArchitecturesGeneral purpose registers architectures

Register-memory (IBM 360, DEC PDP-11, Intel 80386Register-register (load-store) (CDC6600, MIPS, DEC alpha)

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Types ofArchitecture

SourceOperands

Destination

Stack Top two

elements instack

Top of stack

Accumulator Accumulator (1)

Memory (other)

Accumulator

Register set Register or

Memory

Register or

Memory

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Comparison of Architectures

Consider the operation: C = A + B

Stack Accumulator Register-Memory Register-Register

Push A Load A Load R1, A Load R1, A

Push B Add B Add R1, B Load R2, B

Add Store C Store C, R1 Add R3, R1, R2

Pop C Store C, R3

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Classification of Operations

Data TransferLoad, store, mov

Data Manipulation ArithmeticAdd, subtract, multiply, divide

Signed, unsigned, integer, floating-point

Logical - Conjunction, disjunction, shift left, shift

right

Status manipulation

Control Transfer

Conditional Branch Branch on equal, not equal

Set on less than

Unconditional Jump

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Instruction Format

Instruction length needs to be in multiples of

bytes.

Instruction encoding can be:

Variable or Fixed

Variable encoding tries to use as few bits to

represent a program as possible:

But at the cost of complexity of decoding

Alpha, ARM, MIPS instructions:

Operationand Modes

Addr1 Addr2 Addr3

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Addressing Modes

Addressing modes

describe how aninstruction can findthe location of itsoperands

Effective address =actual memoryaddress specified byan addressing mode

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Addressing Modes

INHERENT (0-address) OPCODE

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Immediate Addressing

Operand is part ofinstructionOperand = address fielde.g. ADD 5Add 5 to contents of

accumulator5 is operandNo memory reference to

fetch dataFastLimited range

OPCODE

OPERAND

OPERAND

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ABSOLUTE (DIRECT)

Address field contains address of

operand Effective address (EA) = address field (A)

e.g. ADD A

Add contents of cell A to accumulator

Look in memory at address A for operand

Single memory reference to access data

No additional calculations to work out

effective address Limited address

OPCODE

ADDRESS

OPERAND

MEMORY

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REGISTER

Operand is held inregister named inaddress filed

EA = R

Limited number ofregisters

Very small addressfield needed

Shorter instructions

Faster instruction fetch

Register Addressing

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Register Addressing

No memory access

Very fast execution Very limited address space Multiple registers helps performance Requires good assembly programming

or compiler writing N.B. C programming register int a; c.f. Direct addressing

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Indirect Addressing

Memory cell pointed to by address field contains

the address of (pointer to) the operand EA = (A)

Look in A, find address (A) and look there for

operand e.g. ADD (A)

Add contents of cell pointed to by contents of A to

accumulator OPCODE

ADDRESS

A2

MEMORY

OPERAND A2

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Indirect Addressing

Large address space

2n where n = word length

May be nested, multilevel, cascaded

e.g. EA = (((A)))

Draw the diagram yourself

Multiple memory accesses to find operand

Hence slower

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Register Indirect Addressing

OPCODE RPkREGISTER

PAIRS

(RPk)

MEMORY

OPERAND

EA = (R)

Operand is in memory cell pointed toby contents of register R

Large address space (2n)

One fewer memory access thanindirect addressing

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PAGED

Addressing Modes

OPCODE

OFFSET

OPERAND

ADDRESS

DIRECT-PAGE

REGISTER

MEMORY

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Displacement Addressing

EA = A + (R)

Address field hold two values

A = base value

R = register that holds displacement or vice versa

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Index Addressing

A = base

R = displacement EA = A + R

Good for accessing arrays

EA = A + R

R++

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BASED

BASED-INDEXED

OPCODE

MEMORY

CONSTANT

+

BASE

REGISTER

OPERAND

Addressing Modes

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Relative Addressing

A version of displacement addressing

R = Program counter, PC

EA = A + (PC)

i.e. get operand from A cells from current location

pointed to by PC locality of reference & cache usage

OPCODE

DISPLACEMENT

+

PROGRAM COUNTER

MEMORY

OPERAND

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STACK

Empty

Empty

Empty

SP A

Empty

Empty

SP

PUSH A

A

B

Empty

SP

PUSH B

Empty

A

B

Empty

SP

POP B

Empty

Addressing Modes

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RISC/CISCControversy

RISC: Reduced Instruction Set Computer

CISC: Complex Instruction Set ComputerGenesis of CISC architecture:

Implementing commonly used instructions in

hardware can lead to significant performance

benefits. For example, use of a FP processor can lead to

performance improvements.

Genesis of RISC architecture:

The rarely used instructions can be eliminated tosave chip space --- on chip cache and large

number of registers can be provided.

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Featuresof A CISC Processor

Rich instruction set: some simple, some very complex

Complex addressing modes: Orthogonal addressing(Every possible

addressing mode for every instruction).

Many instructions take multiple cycles:Large variation in CPI

Instructions are of variable sizes

Small number of registers

Microcode control No (or inefficient) pipelining

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TheCISC Philosophy

One instruction could do the work of several

instructions. For example, a single instruction could load

two numbers to be added, add them, and thenstore the result back to memory directly.

Many versions of the same instructions weresupported; Different versions did almost the same thing

with minor changes. For example, one version would read two

numbers from memory, and store the result ina register. Another version would read onenumber from memory and the other from aregister and store the result to memory.

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Featuresof a RISC Processor

Small number of instructions

Small number of addressing modes

Large number of registers (>32)

Instructions execute in one or two clock cycles

Uniformed length instructions and fixedinstruction format.

Register-Register Architecture:

Separate memory instructions (load/store)

Separate instruction/data cache

Hardwired control

Pipelining (Why CISC are not pipelined?)

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Early RISC Processors

1987 Sun SPARC

1990 IBM RS 6000

1996 IBM/Motorola PowerPC

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CISC vs. RISC Organizations

Main Memory Main Memory

Microprogrammed

Control Unit

Microprogrammed

Control Memory

Cache

Hardwared

Control Unit

Instruction

Cache

Data

Cache

(a) CISC Organization (b) RISC Organization

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Why Does RISC Lead to Improved Performance?

Increased GPRs (Also, Register Windows)

leads to decreased data traffic to memory.

Register-Register architecture leads to more

uniform instructions:

Efficient pipelining becomes possible.

However, large instruction memory traffic:

Because of larger number of instructions.

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RISC-Like instructions can be scheduled to achieveefficiency: Either by compiler or By hardware (Dynamic instruction scheduling).

Suppose we need to add 2 values and store theresults back to memory.

In CISC:

It would be done using a single instruction. In RISC:

4 instructions would be necessary.

Why Does RISC Lead to Improved Performance?

C St d

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Case Study

MIPS Instruction Set architecture

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RegistersMIPS has 32 architected 32-bit registersEffective use of registers is key to program performance

Data Transfer32 words in registers, millions of words in main memoryInstruction accesses memory via memory addressAddress indexes memory, a large single-dimensional array

AlignmentMost architectures address individual bytesAddresses of sequential words differ by 4

Words must always start at addresses that are multiples of 4

Operands in MIPS

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r0: always 0r1: reserved for the assemblerr2, r3: function return values

r4~r7: function call argumentsr8~r15: caller-saved temporariesr16~r23 callee-saved temporariesr24~r25 caller-saved temporariesr26, r27: reserved for the operating systemr28: global pointerr29: stack pointerr30: callee-saved temporariesr31: return address

Register Usage ConventionsRegisters

MIPS has 32 architected 32-bit registers

Effective use of registers is key to program performance

D t T i MIPS

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Data Types in MIPS

Data and instructions are both represented in bits32-bit architectures employ 32-bit instructionsCombination of fields specifying operations/operands

MIPS operates on:32-bit (unsigned or 2s complement) integers),32-bit (single precision floating point) real numbers,

64-bit (double precision floating point) real numbers;32-bit words, bytes and half words can be loaded into GPRsAfter loading into GPRs, bytes and half words are either zeroor sign bit expanded to fill the 32 bits;Only 32-bit units can be loaded into FPRs and 32-bit real

numbers are stored in even numbered FPRs.64-bit real numbers are stored in two consecutive FPRs,starting with even-numbered register.Floating-point numbers IEEE standard 754 float: 8-bit exponent, 23-bitsignificand double:11-bit exponent, 52-bit significand

MIPS M O i ti

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MIPS Memory Organization

MIPS supports byte addressability:

It implies that a byte is the smallest unit with its

address;

32-bit word has to start at byte address that is

multiple of 4;Thus, 32-bit word at address 4n includes four bytes

with addresses: 4n, 4n+1, 4n+2, and 4n+3.

16-bit half word has to start at byte address that is

multiple of 2; Thus, 16-bit word at address 2n includes

two bytes with addresses: 2n and 2n+1.

It implies that an address is given as 32-bit unsigned

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MIPS Instruction Formats

R-Type Instruction Fields

op: basic operation of instruction, called the opcoders, rt: first, second register source operandrd: register destination operandshamt: shift amount for shift instructionsfunct: specifies a variant of the operation, calledfunct ion code

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I-Type Instruction Fields

Opcode specifies instruction format

J-Type Instruction Fields

MIPS Instruction Formats

MIPS Addressing Modes

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Register Addressing

Operand is a register (e.g., add $s2, $s0, $s1)

Base or Displacement AddressingOperand is at memory location whose address is sumof register and constant (e.g., lw $s1, 8($s0))


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Immediate Addressing

Operand is constant within instruction (e.g., addi $s1,$s0, 4)


PC-Relative Addressing

Address is sum of PC and constant within instruction(e.g., beq $s0, $s1, 16)


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Pseudo-direct Addressing

Address is 26 bits of constant within instructionconcatenated with upper 6 bits of PC (e.g., j 1000)

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Survey of MIPS Instruction Set

Arithmetic

Additionadd $s1, $s2, $s3 # $s1 = $2 + $s3, overflow detectedaddu $s1, $s2, $s3 # $s1 = $s2 x $s3, overflowundetected

Subtractionsub $s1, $s2, $s3 # $s1 = $s2 - $s3, overflow detectedsubu $s1, $s2, $s3 # $s1 = $s2 - $s3, overflowundetected

Immediate/Constantsaddi $s1, $s2, 100 # $s1 = $s2 + 100, overflow detectedaddiu $s1, $s2, 100 # $s1 = $s2 + 100, overflowundetected

S f MIPS I i S

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Multiplymult $s2, $s3 # Hi, Lo = $s2 x $s3, 64-bit signed productmultu $s2, $s3 # Hi, Lo = $s2 x $s3, 64-bit unsignedproduct

Dividediv $s2, $s3 # Lo = $s2/$s3, Hi = $s2 mod $s3divu $s2, $s3 # Lo = $s2/$s3, Hi = $s2 mod $s3,unsigned

Ancillarymfhi $s1 # $s1 = Hi, get copy of Himflo $s1 # $s1 = Lo, get copy of low

Arithmetic


S f MIPS I t ti S t

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Boolean Operationsand $s1, $s2, $s3 # $s1 = $s2 & $s3, bit-wise ANDor $s1, $s2, $s3 # $s1 = $s2 | $s3, bit-wise OR

Immediate/Constantsandi $s1, $s2, 100 # $s1 = $s2 & 100, bit-wise ANDori $s1, $s2, 100 # $s1 = $s2 | 100, bit-wise OR

Shiftingsll $s1, $s2, 10 # $s1 = $s2 > 100, shift right


Logical

S f MIPS I t ti S t

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Load Operationslw $s1, 100($s2) # $s1 = Mem($s2+100), load wordlbu $s1, 100($s2) # $s1 = Mem($s2+100), load bytelui $s1, 100 # $s1 = 100 * 2^16, load upper imm.

Store Operationssw $s1, 100($s2) # Mem[$s2+100] = $s1, store wordsb $s1, 100($s2) # Mem[$s2+100] = $s1, store byte


Data Transfer

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S f MIPS I t ti S t

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Floating Point Operations

Arithmetic{add.s, sub.s, mul.s, div.s} $f2, $f4, $f6 # single-precision{add.d, sub.d, mul.d, div.d} $f2, $f4, $f6 # double-precisionFloating-point registers are used in even-odd pairs, using evennumber register as its name

Data Transfer{lwc1, swc1} $f1, 100($s2)Transfer data to/from floating-point register file

Conditional Branch{c.lt.s, c.lt.d} $f2, $f4 # if ($f2 < $f4), cond=1, else cond=0{bclt, bclf} 25 # if (cond==1/0), go to PC+4+100

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lec-1-2 ISA

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