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Electrical and ComputerEngineering

Digital Logic Design

ECE112

Lecture 34

[Monday 11/30/09]

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Assignment for the next few weeks

Homework assignment is posted on the

website. Reading assignment is to finish Chapter 8

Labs to be performed for the next 2 weeksare Lab #7, ECE112_Final Project.

Your assignment on the final project is to

design the project, implement it,

demonstrate it to the instructor, and write a

project report.

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Final Project Description

(Was due on Monday 11/23/089 by COB) For those of you who turned it in, thank you and

continue on your projects. For those of you who didnt turn in a description,

youve lost a few points off the project. And I

have no idea if the project you are doing isadequate or not.

It should be some type of FSM (Finite State

machine). It can be one from the list I posted, or one that you

would like to build. But whatever it is, I would

like to know what is is and what its going todemonstrate

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Today

Continue our discussion of

Synchronous Sequential Networks or

as they are commonly referred to

Finite State Machines

(chapter 8)

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Figure 8.22. Sequences of input and output signals.

Clock cycle: t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10w: 0 1 0 1 1 0 1 1 1 0 1

z : 0 0 0 0 1 0 0 1 1 0 0

Note new specification: Output Z=1 if Input w =1 for twoclock ticks and is currently 1. Specification looks like this

table:

Since output depends on both Present State

Variables and the Input it is a Mealy machine.

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Output can change Asynchronously

Since the memory can only change on clocksynchronously, in the Moore machine the

output could only change synchronouslywith the clock

In the Mealy machine since the input signalis also used in creating the output via the

OFL, and since the input can changeasynchronously, the output of the circuitcould change asynchronously

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Mealy MachineInput signals are applied to both the input circuits

and the output circuits.

Combinational

circuitFlip-flops

Clock

Q

WZ

Combinationalcircuit

Input Forming Logic

IFL

Output Forming Logic

OFL

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Figure 8.23. State diagram of an FSM that realizes the task in

Figure 8.22.

A

w 0= z 0=

w 1= z 1=Bw 0= z 0=

Reset

w 1= z 0=

Note in the Mealy machine, the output is not shown in the state

(circle), but rather on the transition along with the input since

the output Z is dependent on both the Memory and Input.

Note the number of states

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Figure 8.36. VHDL code for the

Mealy machine of Figure 8.23.

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY mealy IS

PORT ( Clock, Resetn, w : IN STD_LOGIC ;

z : OUT STD_LOGIC ) ;

END mealy ;

ARCHITECTURE Behavior OF mealy IS

TYPE State_type IS (A, B) ;

SIGNAL y : State_type ;

BEGIN

PROCESS ( Resetn, Clock )

BEGINIF Resetn = '0' THEN

y

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Figure 8.39. Block diagram for the synchronous

serial adder. ( Mealy-Type FSM)

Sum A B+=

Shift register

Shift register

AdderFSM Shift register

B

A

a

b

s

Clock

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Figure 8.40. State diagram for the serial adder FSM.

G

00 1

11 110 0

01 0

H10 101 1

00 0

carry-in 0=

carry-in 1=

G:

H:

Reset

11 0

ab s( )

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Figure 8.42. State-assigned table for Figure 8.41.

PresentNext state Output

state ab =00 01 10 11 00 01 10 11

y Y s

0 0 0 0 1 0 1 1 0

1 0 1 1 1 1 0 0 1

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Figure 8.43. Circuit for the adder FSM in Figure 8.39.

Fulladder

a

b

s

D Q

Q

carry-out

Clock

Reset

Y y

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Figure 8.39. Block diagram for the serial adder.

( Mealy-Type FSM)

Sum A B+=

Shift register

Shift register

AdderFSM Shift register

B

A

a

b

s

Clock

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Figure 8.45. State table for the Moore-type serial adder FSM.

Present Nextstate Outputstate

ab =00 01 10 11 s

G0 G0 G1 G1 H0 0

G1 G0 G1 G1 H0 1

H0 G1 H0 H0 H1 0

H1 G1 H0 H0 H1 1

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Figure 8.46. State-assigned table for Figure 8.45.

PresentNextstate

state ab =00 01 10 11 Output

y2y1 Y2Y1 s

00 0 0 01 0 1 10 0

01 0 0 01 0 1 10 1

10 0 1 10 1 0 11 011 0 1 10 1 0 11 1

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Figure 8.47. Circuit for the Moore-type serial adder FSM.

Fulladder

a

b

D Q

QCarry-out

Clock

Reset

D Q

Q

s

Y2

Y1Sum bit

y2

y1

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Figure 8.48. Code for a left-to-right shift register with an enable input.

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

-- left-to-right shift register with parallel load and enable

ENTITY shiftrne ISGENERIC ( N : INTEGER := 4 ) ;

PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

L, E, w : IN STD_LOGIC ;

Clock : IN STD_LOGIC ;

Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END shiftrne ;

ARCHITECTURE Behavior OF shiftrne IS

BEGIN

PROCESS

BEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF E = '1' THEN

IF L = '1' THEN

Q

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Figure 8.49.a VHDL code for the serial adder (Part a).

1 LIBRARY ieee ;

2 USE ieee.std_logic_1164.all ;

3 ENTITY serial IS

4 GENERIC ( length : INTEGER := 8 ) ;5 PORT ( Clock : IN STD_LOGIC ;

6 Reset : IN STD_LOGIC ;

7 A, B : IN STD_LOGIC_VECTOR(length-1 DOWNTO 0) ;

8 Sum : BUFFER STD_LOGIC_VECTOR(length-1 DOWNTO 0) );

9 END serial ;

10 ARCHITECTURE Behavior OF serial IS

11 COMPONENT shiftrne

12 GENERIC ( N : INTEGER := 4 ) ;

13 PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

14 L, E, w : IN STD_LOGIC ;

15 Clock : IN STD_LOGIC ;

16 Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;17 END COMPONENT ;

18 SIGNAL QA, QB, Null_in : STD_LOGIC_VECTOR(length-1 DOWNTO 0) ;

19 SIGNAL s, Low, High, Run : STD_LOGIC ;

20 SIGNAL Count : INTEGER RANGE 0 TO length ;

21 TYPE State_type IS (G, H) ;

22 SIGNAL y : State_type ;

continued in Part b

23 BEGIN

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Figure 8.49.b VHDL code for the serial adder (Part b).

23 BEGIN

24 Low length)

28 PORT MAP ( B, Reset, High, Low, Clock, QB ) ;

29 AdderFSM: PROCESS ( Reset, Clock )

30 BEGIN31 IF Reset = '1' THEN

32 y

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Example on board

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Now lets look at another example

It is a sequence detector

We will compare Moore and Mealyimplementations.

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First: A Moore FSM that detects the

sequence 1011

This State machine outputs a 1 if thesequence 1011 is detected

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Sequence Detector that detects 1011 and

outputs a logic 1 after sequence is detected.

(3 flip-flops are required for implementation)

Note that output is 1 after 1011 is detected

and output stays 1 for a full clock cycle.

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0

1clock

0

1Input

0

1Moore

Output

1 1 10 0

Rising edge of clock shown

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Now: A Mealy FSM that detects the

sequence 1011

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Sequence Detector that detects 1011 and outputs a

logic 1 when sequence is detected.

(Only 2 flip-flops are required to implement this.)

Note that output is 1 on last bit in the detected

sequence. And depending on how long input is 1

determines how long output will remain as a logic 1.

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0

1clock

0

1Input

0

1Mealy

Output

1 1 10 0

Rising edge of clock shown

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The rest of the design is left to the

student

But, you can see that the reduction in statesdoes make the design simpler.

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Bottom Line is:

Everything has its price

As we said before, there are always trade-offs

Weve seen this in a couple of examples

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What are the +s and s

Only the application can determine if theattribute is a + or a - .

For example Consider the attributes of each:

Mealy???

Moore??

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What are the +s and s

Mealy???Simpler structure

Moore??

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What are the +s and s

Mealy???Simpler structure

Asynchronous operation

Moore??

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What are the +s and s

Mealy???Simpler structure

Asynchronous operation

Output only valid at transition of clock

Moore??

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What are the +s and s

Mealy???Simpler structure

Asynchronous operation

Output only valid at transition of clock

Moore??

Synchronous operation

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What are the +s and s

Mealy?Simpler structure

Asynchronous operation

Output only valid at transition of clock

Moore??Synchronous operation

Output stable for entire cycle

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0

1clock

0

1Input

0

1Moore

Output

0

1Mealy

Output

1 1 10 0

Rising edge of clock shown

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0

1clock

0

1Input

0

1Moore

Output

0

1Mealy

Output

1 1 10 0

Rising edge of clock shown

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A h l

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Another example

A little more complex - Notthat I expect you to be able

implement this, but just to

show the scope of FSMs

Lets look at a simple computerwith a two bit word.

C t I t

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Computer Inputs

The computer is a two bit computer, that is,it has a 2 bit instruction word x1 and x2

Bit x1 indicates if an instruction is to be

executedx1 = 1 means execute an instruction

x1 = 0 means no execution Bit x2 indicates specifically what the

instruction is:

x2 = 1 means input a number and send it tooutput

x2 = 0 means input a number, multiply it by 2and send it to the output.

Computer (Hardware)

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X1,X2

0 1

1 0

1 1

0 0

Program

FSM

Heres a state diagram of the computer.

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g p

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Now, on to Minimization

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1 0 0 0

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AdderFSM

Clock

Ew

L

EwL

b 7 b 0

a 7 a 0

EwL

EL

Q 3 Q 2 Q 1 Q 0

D 3 D 2 D 1 D 0

Counter

0 0

ResetSum 7 Sum 0

01

01

Run

Figure 8.50. Synthesized serial adder.

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Figure 8.51. State table for Example 8.5.

Present Next state Outputstate

w = 0 w = 1

z

A B C 1

B D F 1

C F E 0

D B G 1E F C 0

F E D 0

G F G 0

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Figure 8.52. Minimized state table for Example 8.5.

Present Nextstate Output

state w = 0 w = 1 z

A B C 1

B A F 1

C F C 0F C A 0

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Figure 8.53. Signals for the vending machine.

D Q

Q

senseN D Q

QClock

N

senseN

senseD

Clock

N

D

(a) Timing diagram

(b) Circuit that generates N

DN

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Figure 8.54. State diagram for Example 8.6.

S1 0

S7 1

DN

D N

S3 0

S6 0

S9 1S8 1

S2 0

S5 1

S4 1

DNDN

DNDN

DN

DN

DN

D

D N

DN

DN

N

Reset

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Figure 8.55. State table for Example 8.6.

Present Next state Outputstate DN =00 01 10 11 z

S1 S1 S3 S2 0

S2 S2 S4 S5 0

S3 S3 S6 S7 0

S4 S1 1

S5 S3 1

S6 S6 S8 S9 0

S7 S1 1

S8 S1 1

S9 S3 1

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Figure 8.56. Minimized state table for Example 8.6.

Present Next state Outputstate DN =00 01 10 11 z

S1 S1 S3 S2 0

S2 S2 S4 S5 0

S3 S3 S2 S4 0

S4 S1 1S5 S3 1