Micro Lec Note1

PowerPoint PresentationAuthor: Burry B. Brey
hsabaghianb @ kashanu.ac.ir Microprocessors 1-*
Microcompiuter and Microprocessor : the 8080 , 8085 , Z-80 Programming , interfacing and trubleshooting
Publisher: Nass
Pub.Date: 1381
Books
The 80x86 IBM PC and compatible computers (Design and interfacing of the IBM PC PS and compatible)
Publisher: Baghani
Pub.Date: 1379
Components of CPU
Micro-computer (u-Computer)
small computer
uP + peripheral I/O + memory specifically for data acquisition and control applications
Microcontroller (uC)
bus is available
RAM is larger than ROM (usually)
A uC
contains a CPU and RAM,ROM ,Prepherals, I/O port in a single IC
internal hardware is fixed
Small power consumption
Applications
uCs are suitable to control of I/O devices in designs requiring a minimum component
uPs are suitable to processing information in computer systems.
uP vs. uC – cont.
Only single chip can be a complete system
interfacing to other devices,
In contrast, similar system that builds from
uP would require a lot of additional units,
such as RAM, UART, I/O , TIMER and etc.
Logic circuit provides limited function for one
single design. In order to change circuit’s
functionality, we need to redesign the circuits.
uC can reprogram and change functionality of
every port, input to output or digital to analog
on the fly.
8051, 68HC11, MSP430, ARM series, and etc.
We may widely divide it with how it is designed
RISC/CISC architecture.
RISC/CISC?
processing data
controlling all of the components which make up the microcomputer system
µP used to sequence executions of instructions that is in memory
uP Fetch , Decode , and Execute the instruction
The internal architecture of the microprocessor is complex.
Registers: Temporary storage locations for program instruction or data.
The Arithmetic Logic unit (ALU): This part of the MPU performs both arithmetic and logical operations
Timing and Control Circuits: that keep all of the other parts of system (Regs, ALU, memory & I/O) working together in the right time sequence
1. Microprocessor Unit (MPU)
2. Program Memory (ROM)
3. Data Memory (RAM)
4. Input / Output ports
The Input/Output (I/O) System
I/O is the link between the MPU and the outside world.
An input port is a circuit through which an external device can send signals (data?) to the MPU.
An output port is a circuit that allows the MPU to send signals (data?) to external devices.
I/O ports connect both digital and analogue devices by DAC and ADC
Bus
A Bus is a common communications pathway used to carry information between the various elements of a computer system
The term BUS refers to a group of wires or conduction tracks on a printed circuit board (PCB) though which binary information is transferred from one part of the microcomputer to another
The individual subsystems of the digital computer are connected through an interconnecting BUS system.
ADDRESS BUS
DATA BUS
CONTROL BUS
Data Bus
The Data Bus carries the data which is transferred throughout the system. ( bi-directional)
Examples of data transfers
Data being read from I/O port going to MPU
Results from MPU sent to Memory
These are called read and write operations
Address Bus
An address is a binary number that identifies a specific memory storage location or I/O port involved in a data transfer
The Address Bus is used to transmit the address of the location to the memory or the I/O port.
The Address Bus is unidirectional ( one way ): addresses are always issued by the MPU.
Control Bus
The Control Bus: is another group of signals whose functions are to provide synchronization ( timing control ) between the MPU and the other system components.
Control signals are unidirectional, and are mainly outputs from the MPU.
Example Control signals
To store programs
Main memory Types
ROM : read only memory. Contains program (Firmware). does not lose its contents when power is removed (Non-volatile)
RAM: random access memory (read/write memory) used as variable data, loses contents when power is removed volatile. When power up will contain random data values
ROM remembers the data, even after power cycled
Typically, when the power is turned on, the microprocessor will start fetching instructions from the still-remembered program in ROM (bootstrap )
On a PC, the ROM is called the BIOS (Basic Input/Output System). When the microprocessor starts, it begins executing instructions it finds in the BIOS. The BIOS instructions do things like test the hardware in the machine, and then it goes to the hard disk to fetch the boot sector. This boot sector is another small program, and the BIOS stores it in RAM after reading it off the disk. The microprocessor then begins executing the boot sector's instructions from RAM. The boot sector program will tell the microprocessor to fetch something else from the hard disk into RAM, which the microprocessor then executes, and so on. This is how the microprocessor loads and executes the entire operating system
Masked ROM or just ROM
PROM or programmable ROM(once only)
EPROM (erasable via ultraviolet light)
Flash (can be erased and re-written about 10000 times, usually must write a whole block not just 1 byte or 2 bytes, slow writing, fast reading)
EEPROM (electrically erasable read-only memory, also known as EEROM—both reading and writing are very slow but can program millions of times…useless for storing a program but good for say configuration information.
A0-Am
D0-Dn
16 kbit
2 kbyte
32 kbit
4 kbyte
64 kbit
8 kbyte
Two type of is available :
Static RAM(SRAM): ff base, fast, expensive, low cap/vol, applied for cache , no refresh
Dynamic RAM (DRAM): cap base, slow , low cost high capacity/volume , applied for main memory(pc) need refresh.
RAM stands for random-access memory. RAM contains bytes of information, and the microprocessor can read or write to those bytes depending on whether the RD or WR line is signaled. One problem with today's RAM chips is that they forget everything once the power goes off. That is why the computer needs ROM
Data bus is
Microprocessors
Microprocessors come in all kinds of varieties from the very simple to the very complex
Depend on data bus and register and ALU width uP could be 4-bit , 8-bit , 16-bit, 32-bit , 64-bit
We will discuss two sample of it
Z80 as an 8-bit uP
and 8086/88 as an 16-bit uP
All uPs have
the address bus
the data bus
Internal and External Bus
Internal bus is a pathway for data transfer between registers and ALU in the uPs
External bus is available externally to connect to RAM, ROM and I/O
Int. and Ext. Bus width may be different
For example
In 8088 Int. Bus is 16-bit , Ext. bus is 8-bit
In 8086 Int. Bus is 16-bit , Ext. bus is 16-bit
Data Width is the width of the ALU. An 8-bit ALU can add/subtract/multiply/etc. two 8-bit numbers, while a 32-bit ALU can manipulate 32-bit numbers. An 8-bit ALU would have to execute four instructions to add two 32-bit numbers, while a 32-bit ALU can do it in one instruction. In many cases, the external data bus is the same width as the ALU, but not always. The 8088 had a 16-bit ALU and an 8-bit bus, while the modern Pentiums fetch data 64 bits at a time for their 32-bit ALUs.
AD0..AD7 , A8..A15 , A19/S6, A18/S5, A17/S4, A16/S3 : 20 -bit Address Bus
MN/MX’ (input) : Indicates Operating mode
READY (input , Active High) : take uP to wait state
CLK (input) : Provides basic timing for the processor
RESET (input, Active High) : At least 4 clock cycles Causes the uP immediately
terminate its present activity.
HLDA (output , Active High) : Hold Ack
INTR (input , Active High) : Interrupt request
INTA’ (output , Active Low) : Interrupt Acknowledge
NMI (input , Active High) : Non-maskable interrupt
8086 Pin Description
DEN’ (output) : Data Enable. It is LOW when processor wants to
receive data or processor is giving out data (to74245)
DT/R’ (output) : Data Transmit/Receive.
When Low, data is from memory to uP (to74245 dir)
IO/M’ (output) : If High uP access I/O Device.
If Low uP access memory
RD’ (output) : When Low, uP is performing a read operation
WR’ (output) : When Low, uP is performing a write operation
ALE (output) : Address Latch Enable , Active High
Provided by uP to latch address
When HIGH, uP is using AD0..AD7, A19/S6,
A18/S5, A17/S4, A16/S3 as address lines
Z80 CPU Pin Assignment
Used for accessing the memory and I/O ports
During the refresh cycle the I is put on this bus.
D7-D0 :
Data Bus (input/output, active high, 3-state). Used for data exchanges with memory, I/O and interrupts.
RD:
Read (output, active Low, 3-state) indicates that the CPU wants to read data from memory or I/O
WR:
Write (output, active Low, 3-state) indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O location.
IORQ
M1
Machine Cycle One (output, active Low).
Together with MREQ indicates opcode fetch cycle Together with IORQ indicates an Int Ack cycle
RFSH
Lower 7-bits address is refresh address to DRAM
Interrupt Request is generated by I/O devices.
Checked at the end of the current instruction
If flip-flop (IFF) is enabled.
NMI
Independent of the status of IFF
Forces the CPU to restart at location 0066H.
higher priority than NMI
machine cycle.
forces the CPU address bus, data bus, and MREQ, IORQ, RD, and WR to high-imp.
BUSACK
Bus Acknowledge (output, active,Low)
indicates to the requesting device that address, data, and control signals
MREQ, IORQ, RD, and WR have entered their high-impedance states.
Resets the IFF
Clears the PC and registers I and R
Sets the interrupt status to Mode 0. During reset time, the address and data bus go to a high-impedance state And all control output signals go to the inactive
state.
must be active for a minimum of three full clock cycles before the reset operation is complete.
Two sets of six general-purpose registers
may be used individually as 8-bit A F B C D E H L (A’ F’ B’ C’ D’ E’ H’ L’)
or in pairs as 16-bit registers AF BC DE HL (AF’ BC’ DE’ HL’)
The Alternative registers (A’ F’ B’ C’ D’ E’ H’ L’) not visible to the programmer but can access via:
EXX (BC)<->(BC') , (DE)<->(DE') , (HL)<->(HL')
EX AF, AF ’ (AF)<->(AF')
index registers (IX) and (IY) are 16-bit memory pointers
16 bit stack pointer (SP)
Program counter (PC)
Program counter (PC)
PC points to the next opcode to be fetched from ROM
when the µP places an address on the address bus to fetch the byte from memory, it then increments the program counter by one to the next location
Special purpose registers
S Sign Flag (1:negativ)*
Z Zero Flag (1:Zero)
H Half Carry Flag (1: Carry from Bit 3 to Bit 4)**
P Parity Flag (1: Even)
V Overflow Flag (1:Overflow)*
N Operation Flag (1:previous Operation wassubtraction)**
C Carry Flag (1: Carry from Bit n-1 to Bit n,
with n length of operand)
*: 2-complement number representation
DAA - Decimal Adjust Accumulator
Adjusts the content of the Accumulator A for BCD addition and subtraction
operations such as ADD, ADC, SUB, SBC, and NEG according to the table:
before DAA
after DAA
and “T-states”
Instruction cycle is the time taken to complete the execution of an instruction
Machine cycle is defined as the time required to complete one operation of accessing memory, accessing IO, etc.
T-state = 1/f (f:Z80 Clock Frequency)
f= 4MHZ T-state=0.25 uS
Basic CPU Timing Example
Is increased at every first machine cycle (M1).
Bit 7 of it is never changed by this; only the lower 7 bits are included in the addition. So bit 7 stays the same
Bit 7 can be changed using the LD R,A instruction.
LD A,R and LD R,A access the R register after it is increased
R is often used in programs for a random value, which is good but of course not truly random.
the block instructions decrease the PC with two, so the instructions are re-executed.
During I/O operations a single wait state is automatically inserted
Non-Maskable Interrupt Request Operation
This simplifies the external interfacing hardware
DRAM consists of MOS transistors, which store Information as capacitive charges; each cell needs to be periodically refreshed
During T3 and T4 (when Z80 is performing internal ops), the low order address is used to supply a 7-bit address for refresh
Wait Signal
the Z80 samples the wait signal during T2 if low then Z80 adds wait
states to extend the machine cycle
used to interface memories with slow response time
Slow memory is low cost
non mask-able (NMI)
mask-able(INT)
IM 0 sets Interrupt mode 0
Interrupt Modes
Mode 0:
An 8 bit opcode is Fetched from Data BUS and executed
The source interrupt device must put 8 bit opcode at data bus
8 bit opcode usually is RST p instructions
Mode 1:
Mode 2:
A jump is made to address (register I × 256 + value from interrupting device that puts at bus)
I is high 8 bit of interrupt vector
Value is low 8 bit of interrupt vector
Z80 CPU Instruction Description
158 different instruction types
Instruction groups
Jump, Call, and Return
Relative Addressing
Extended Addressing
Absolute jump
2 byte opcode
1 byte displacement
ADD E
ADD (HL)
Bit Addressing
SET 3,A
RES 7,B
CPU 8 bit data bus 8 bit data width
Generally should be connected
If only one RAM chip Full size (64 kb capacity)
RAM
A15 composed with MREQ
RAM
There is two 32 kb RAM
Problem: Bus Conflict. The two memory chips will provide data at the same time when microprocessor performs a memory read.
Solution: Use address line A15 as an “arbiter”. If A15 outputs a logic “1” the upper memory is enabled (and the lower memory is disabled) and vice-versa.
A15 applied to select one RAM chip
Two RAM area is from 0000h to 7FFFh (RAM1)
and 8000h to FFFFh (RAM1)
RAM
ROM doesn’t have wr signal
ROM
A14 and A15 applied to chip selection
ROM
AAAA 1198 10
Empty area
0000h 3FFFh
ROM 16k
4000h 7FFFh
RAM1 16k
8000h BFFFh
RAM2 16k
C000h FFFFh
RAM3 16k
Read op. returns FFh value (usualy)
Write op. cann’t store any value on it
0000h 3FFFh
Read op. returns FFh value (usualy)
Write op. cann’t store any value on it
0000h 3FFFh
Full (exhaust) Decoding
All of the address lines are connected to any memory/device to perform selection
Absolute address : any memory location has one address
Partial Decoding
When some of the address lines are connected the memory/device to perform selection
Using this type of decoding results into roll-over addresses (fold back or shading).
roll-over address : any memory location has more than one address
Then doesn’t play any role in addressing
What is the Memory and Address Bit map?
RAM
For example first RAM location has addresses:
0000h
1000h
2000h
3000h
A13 has no connection
ROM
AAAA 1111 5432
AAAA 1198 10
2147
RWM
D0
2147
RWM
Z80 Input Output
Z80 at most could have 256 input port and 256 output
8 bit port address is placed on A7–A0 pin to select the
I/O device
Content of A is data
OUT (C), r
r is a data register
IN A, (n)
Data is transfered to A
IN r (C)
Remember IO read/write cycle
OUT (03), A
Z80
CPU
A14
A0
A
1
5
8088
Minimum
Mode
A18
A0
A
1
5
8088
Minimum
Mode
A18
A0
D7 - D0
Q7 - Q0
1 MB
What are the memory locations of a 1MB (220 bytes) Memory?
Example: 34FD0
A19 to A0 (HEX)
Don’t connect it
What is the difference?
512 kB Memory Map
Don’t connect it
A19 is not connected to the memory so even if the 8088 microprocessor outputs a logic “1”,the memory cannot “see” it.
A19=0 is the same as A19=1 for Memory
Connect to cs
00000h 7FFFFh
512k Mem
80000h FFFFFh
512k Mem’
00000h 7FFFFh
512k Mem
80000h FFFFFh
2 512 kB memory
What are the memory locations of two consecutive 512KB (219 bytes) Memory?
AAAA 1111 9876
AAAA 1111 5432
AAAA 1198 10
the 8088 Microprocessor
the 8088 Microprocessor
AAAA 1111 9876
AAAA 1111 5432
AAAA 1198 10
8088
Minimum
Mode
A12
A0
8088
Minimum
Mode
A12
A0
8088
Minimum
Mode
A12
A0
AAAA 1111 9876
AAAA 1111 5432
AAAA 1198 10
74138
Y0
Y1
Y2
Y3
Y6
Y4
Y7
Y5
C
B
A
G2A
G2B
G1
2764
EPROM
CONTROL
SECTION
± k
16

Micro Lec Note1

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