THPM 1-8

Semiconductor Pressure Sensor Based on FET Structure tysko J.M.’), Jachowicz R.S.’), Krzycki M.A.”

1) Institute of Electron Technology, Al. Lotnik6w 32/46, 02-668 Warszawa, Poland, E-mail: jmlysko@vax5.ite.waw.pl 2) Institute of Electronics Fundamentals, Warsaw University of Technology, ul. Nowowiejska 15/19, 00-665 Warszawa, Poland.

E-mail: rsjach@ipe.pw.edu.pl

Abstract - As a next step in capacitive pressure sensor development [l-31, a new sensor structure based on Field Effect Transistor is proposed [4]. Similar devices were presented by Suminto et.al. [SI, Gergintschew et. al. [6], Graf et.al. [7], Yoshikawa et.al. [8]. The sensor build up on active FET structure, has a big advantage in reference to the semiconductor capacitive sensors. Its voltage output signal (or current signal) can be simply measured in contrary to relatively difficult measure- ments of capacitance.

An other sensor advantage is because of one side wafer processing during sensors fabrication [l]. The sensor construction as well as details of sensor fabrica- tion technology has been described in the report. The results of computer simulation of the sensor have been discussed in this paper, too. High sensor pressure sensitivity and relatively low sensor dependence on temperature are very important measurement features of the PS-FET sensors.

CONSTRUCTION AND OPERATION

Schematic layout arrangement of the PS-FET - pressure sensitive field effect transistor is shown on Fig.1, and the sensor cross-sectional view is shown on Fig.2. The device construction does not require, as usually for semiconductor pressure sensors, any extra- ordinary steps during fabrication process i.e. deep substrate etching from back side of the wafer to form diaphragm, silicon-to-glass or -to-silicon bonding to form sensor chamber [9], diaphragm positioning and housing [8], etc. The PS-FET silicon chip is a comple- tely monolithic mechanoelectronic device, consisting of four transistor terminals (into substrate, source, drain and gate), the elastic diaphragm and micro-chamber closed to the external gas pressure. The chip dimensions are of 0.38 mm X 0.50 mm x 0.75 mm. The most of its active surface is occupied by the bonding pads (100 pm X 100 pm, each).

The PS-FET square diaphragm area is of 0.01 mm2. It consists of the three LPCVD-type layers : 0.1 pm- thick silicon nitride, 0.53 pm-thick polysilicon, 0.15 pm-thick silicon nitride. Arsenide doped part of this

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1 Fig. 1 : Layout arrangement of PS-FET sensor masks.

polysilicon membrane serves as the transistor gate elec- trode and conductive path. The PS-FET chamber is located just in between the diaphragm and the silicon substrate (1.0 pm separation). The chamber is filled by the gas under atmospheric pressure, and closed by the APCVD-type oxide layers. The area between the transistor source and drain (n+-type regions in the p- type silicon substrate) may be doped in the separate litography and ion implantation steps, to estabilish the transistor channel with required transistor threshold voltage. All transistor electrodes, as well as the p-type substrate, have conductive paths with contact windows in the dielectric layers, leading to the individual metal bonding pads.

Electrical operation of the PS-FET is similar to the operation of the standard field effect transistor. A gate voltage influences on the transistor current I, flowing through the channel. From the other hand, the pressure under measurement causes sensor diaphragm deflection towards the channel. This gate-to-channel distance change influences transistor drain current Ids, similarly as gate voltage U,, changes (see Fig.6). The sensor is well protected against overload pressure influence. When applied pressure exceedes the sensor operation range, the sensor membrane contacts to the substrate (transistor channel) and a fulcrum in the diaphragm center significantly stops its further deflection.

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Fig. 2 : Cross-sectional views of the PS-FET sensor, ( I ) - phosphosilicate glass (PSG) APCVD layer, (2) - SiO, APCM) layer, (3) - Si,N, LPCVD layer, (4) - sensors cavity, (5) - drain (n'), (6) - SiO, thermal layer, (7) - poly-Si gate, (8) - Si,N, L P m layer, (9) - source (n'). (IO) - mono-Si substrate, (11) - metal contact to the gate electrode, (12) - poly-Si undoped LPCM) layer, (13) - metal contact to the source electrode.

FABRICATION The PS-FET silicon chips were fabricated with use of

the p < loo>, 5-9 fl Xcm, 3" wafers. All technological steps, typical to the MOS LSI, were performed with use of IC technological line and the photolitography masks with minimum line definition of 10 pm. The sensor fabrication sequence may be divided into three, almost independent, phases : - substrate processes - groove etching, drain, source, channel doping, - chamber and diaphragm formation - sacrificial oxide (doped and undoped) layers deposition and litography , LPCVD diaphragm deposition, gate electrode doping, penetration areas etching, lateral chamber etching throughout the penetration holes, thin oxidation, oxides (doped and undoped) deposition and reflow [l-31, - output electrical uomections formation - contact window litographies, metal deposition and litography, sintering.

The PS-FET fabrication sequence requires nine photolitbgraphy steps (9 masks) performed from the only one side of the wafers [l], as in the typical integrated circuits). The main improvements of the recent technology, in contrary to earlier construction of the capacitive pressure sensor [l-31, are : - metal movable electrode on the double silicon nitride layer diqphragm (in previous capacitive sensors - plastic metal electrode disturbed mechanical performance of the sensor diaphragm) was replaced by the triple uniform layer sandwich : silicon nitride, polysilicon, silicon nitride, with arsenide doped zone as a gate electrode,

Fig. 3 : SEA4 microphotogmph of the PS-Fh'Tsensor silicon chip top view.

- transistor type device instead of the capacitive one (simplier output signal measurements).

The one-side wafer processing gives complete MOS LSI and PS-FET technological compatibility. The advantage ot this feature has been used to integrate PS- FET with reference FET for temperature compensation. Fig.3 presents SEM microphotography of the PS-FET top view after technological step - metal-Si and metal- polysilicon contact sintering.

TESTS The PS-FET sensors were tested in the pressure range

of 0 - 200 P a , temperatures range of +2O"C to 80°C and for Uds = 12 V voltage. A pressure was applied to the measurement oil chamber with accuracy of 0.1 % and temperature stability of 0.5"C. The sensors together with reference FET were ,mounted in open ceramic DIP packages. The temperature of measurement chamber was under control with help of platinium thermometer Pt,, placed inside the chamber. The output signals from both the PS-FET sensor as well as from the reference FET were measured by PM2535 type Fluke-Philips voltmeter controlled by IBM 286 personal computer. The measurement data were collected, processed and displayed by the computer.

SIMULATION The numerical simulation of presented PS-FET

structure was performed for both better understanding of sensor performance and sensor structure op- timization. At first the computer program MEMSYM [11] based on finite difference method was used to determine a membrane deflection as a function of pressure. It has been assumed that the edges of mem-

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brane are rigidly clamped and the elastic parameters of membrane are E=1.662x101' N/m2, v=0.062 as a moderate value of the elastic parameters for all mem- brane layers (Si,N,/poly-Si/Si,N,>. Calculations were performed with respect to the model of large deflections of membrane (forces acting in the middle plane were under consideration). Moreover, the model considers also the effect of gas compressions due to sensor cavity volume changes (because of the membrane deflection). For calculations the membrane of 100 pm X 100 pm X 0.78 pm was covered with grid 41 X 41 nodes. The pressure, acting on membrane, varied from 0 to 155 kPa and 1.12 pm maximum membrane deflection was achieved. For PS-FET sensor model, the capacitance C(P) be- tween the transistor gate and channel has been cal- culated. The C(P) capacitance is a function of pressure and can be described in simplified way as:

where: P - applied pressure, A - total surface of electro- des, g - cavity depth, w(x,y,P) - membrane deflection in node (x,y), E - dielectric permitivity of the space between the gate electrode and the channel. The electro- static forces influence and eddy field effect were neglected.

The drain current I, of PS-FET was determined on base of equation (2):

where: Ugs, U,, - gate-source and drain-source voltages respectively, U, - threshold voltage equivalent to regular FET parameter, U, - the voltage which balances electrostatic potential caused by the charge build-in to the membrane, /3 - amplification factor (not depended on pressure change), C, - gate to channel capacitance of equivalent regular FET. For the simulation of the sensor from Fig. 1 and Fig. 2 it was estimated that UT=-3.7 V, U0=6 V, p=0.3 mAN2, C,= 1200 pF/mm2 and U,, was set on 12 V.

Characteristics received from the simulation are shown on Fig. 3 , Fig. 4. There is well seen zero sensor sensitivity on pressure for gate-voltage about 6 V . The results verify existence of the electrical charge which is build-in to the membrane.

EXPERIMENTAL RESULTS

At least 20 PS-FET sensors were under the test. The most of sensors had basic metrological parameters very close themselves.

The PS-FET sensor has typical Ids= f(U,,) characteris- tics as for most unipolar transistors - Fig. 5 . It is well seen on both Fig. 5 and Fig. 6 that the PS-FET device

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Absolute pressure [kPa]

Fig. 4 : Dependence of the I, current as afunction of absolute pressure - simulation results for different gate to drain voltage.

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Fig. 5 The characteristic I,=f(UJ of PS-FETpressure sensor very typical as for regular FET structure.

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Voltage u d s [VI Fig. 6 Pressure changes as a driving factor for the PS- FET device ilustration.

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may be driven equivalently by either U,, voltage or applied pressure.

The basic characteristic of PS-FET sensor L=f(P) shows the highest sensitivity for driving voltage UgS.= -10 V - Fig. 7. Moreover, this experimental characteris- tic is very close to theoretical one from Fig. 4. For both cases the influence of build-in electrical charge into transistor gate is well visible and gives effect of sensor unsensitivity for U,,=6 V. The problem is also well illustrated on Fig. 8 - below U,,=6 V the sensor pressure sensitivity is negative and above this value - positive.

The temperature coefficient of PS-FET sensor is on the level of -0.20 %/K and for the equivalent FET device fabricated in the same process is +0.25 %/K. Opposite sign of both temperature factors gives pos- sibility for advanced temperature compensation.

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Fig. 7 The basic PS-FET sensor characteristic I&=f(P) for direrent driving voltage Us..

Pressure [kPa]

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Fig. 8 An ilustration of the efect of electrical charge build-in to the membrane.

CONCLUSIONS

The pressure sensors based on FET structure have been fabricated by one side wafer processing with standard IC technology.

The sensors show relatively high sensitivity and moderate temperature coefficient. The temperature effect can be simply compensated by reference FET structure.

The theoretical model of the sensor gave good results of simulations.

REFERENCES :

J.M . Lysko, EStolarski, R. S. Jachowicz, "Capaci- tive silicon pressure. sensor based on the one-side wafer processing'', Proc. TRANSDUCERS 'PI Conz, San Francisco - USA, 1991, pp. 685-688, J.Lysko, R.S.Jachowicz, M.Krzycki, "Capacitive semiconductor pressure sensor with floating electrode", submitted to the XIII IMEKO WorM Congress, Italy, 1994, Polish patents no. 158922, 1582256, and patent pending no. P-289385, Polish patent pending no. P-3OOO56, J .T.Suminto, W .H .KO, "Pressure-sensitive insula- ted gate field-effect transistor (PSIGFET)" , Sen- sors M d A c ~ o r s , 1990, vol.A21-23,pp.126-132, Z . Gergintschew , D .Schipanski, P.Pometzky , I.Eisele, B.Flietner, "Simulation of the lateral electrical field for the analysis of threshold voltage instabilities of suspended-gate field effect transis- tors", Sensors and Actuators, 1993, vol.Bl2,

E.Graf, W.Kronast, S.Duhring, B.Muller, A. Stofferl, "Silicon membrane condenser microphone with integrated field-effect transistor", Sensors and Actuators, 1993, vol.A37-38, pp.708-711, A.Yoshikawa, T.Suzuki, "Properties of movable- gate field-effect structure as an electromechanical sensors", J o u m l Acoust. Soc. Am., 1978, vo1.64, J.Bryzek, K.Petersen, J.R.Mallon, L.Christe1, F. Pourahmadi, Silicon Sensors and Microstructures, ed. by Novasensor, Silicon Valley, June 1990, P.Pan, C.Schaefer, "Effects of processing on characteristics of 10-15 nm thermally grown SiO, films", J. Electrochem. Soc., 1986, vo1.133, no.6,

M . Krzycki, R. Jachowicz, J. Lysko, "Modelowanie p6ip~ewodnikowych czujnikdw cidnienia", Elek- tronizacja, 1993, 10, pp. 13-16.

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