109.SD Module 3 Notes

8/9/2019 109.SD Module 3 Notes

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109. Semiconductor Devices Module 3

Department of ECE, VKCET Page 1

Texts and References:

1. Streetman & Banerjee : Solid State Electronic Devices, 6/e, PHI

2. S.M.Sze: Physics of Semiconductor Devices, 3/e, Wiley Eastern

3. V. Suresh Babu: Solid State Devices & Technology, Sanguine, Bangalore, 2005.


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Bipolar Junction Transistor (BJT):

BJT is a three terminal device and the terminals are: emitter (E), base (B) and collector

(C).

Two types of BJT are:

1. npn

2.

pnp

In npn BJT, two n regions are separated by a p region. The structure and symbol of npn

BJT is shown below:

In pnp BJT, two p regions are separated by a n region. The structure and symbol of pnp

BJT is shown below:

The emitter region is typically medium in area and heavily doped, base region is small in

area and lightly doped and collector region is large in area and moderately doped.

BJT has two junctions named emitter-base junction and

collector-base junction. So the device is called bipolar

junction transistor.

Modes of operation:

BJT can operate in different modes according to the biasing

of two junctions. They are:

Modes of

operation

Biasing

ApplicationsEmitter-Base

junction

Collector-Base

junction

Forward active Forward bias Reverse bias Amplifier

Inverse active Reverse bias Forward bias Attenuator

Forward

saturationForward bias

Forward bias

(VEB> VCB)Switch

Inverse

saturationForward bias

Forward bias

(VEB< VCB)Switch

Cut-off Reverse bias Reverse bias Switch

Question:

Part AWhat are the different modes of

operation of BJT?


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Current components and terminal currents in BJT:

Consider the forward active mode of a pnp BJT. i.e.

emitter-base junction under forward biased and

collector-base junction under reverse biased,

The current components in pnp BJT is as shown below:

The different current components in BJT and its reasons are:IpEEmitter current due to injection of hole from

emitter to base.

InE Emitter current due to injection of electron

from base to emitter.

IrBBase current due to recombination of carriers

in base.

IpCCollector current due to injection of holes from emitter to collector through

base.

ICBOReverse saturation current in reverse biased collector-base junction, when

emitter-base junction is open. This current is due to minority carriers and is also

called leakage current in collector-base junction.

There is also terminal currents and its relationship with current components are:

Emitter current IE= IpE+ InE

Collector current IC= IpC+ ICBO

Base current IB= IrB+ InEICBO

For a transistor, current flowing towards the device is +ve, otherwise it is ve. So for

pnp BJT IEis +ve, IBisve (since most of the current is due to IrB) and ICis alsove.

npn BJT is symmetry of pnp, so its IEis -ve, IBand ICis +ve.

The voltage drop and terminal currents in both BJT are shown:

Question:

Part B

Draw the current components in

BJT.

Question:

Part B

List the current components inBJT. How they are related to

terminal currents?


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Basic performance parameters of BJT

The most important parameters in BJT are:

1. Common-base current gain

2. Common-emitter current gain

Two other parameters which defines and are:

1.

Emitter injection efficiency

2. Base transportation factor T

Emitter injection efficiency

It defines that how many carriers are injecting from

emitter to base. For pnp, it is the ratio of emitter current

due to holes injected from emitter to base to the total

emitter current.

It can be expressed as

= = + =

+ This shows that, to achieve maximum injection efficiency,

should be minimum.This can be achieved by keeping the emitter doping concentration maximum with

respect to base doping concentration.

Base transport factor

It defines that how many carriers are transporting from emitter to collector through base. For

pnp, it is the ratio of collector current due to hole to the emitter current due to hole.

It can be expressed as = We can express

=

+

, then

= + =

+

Question:

Part ADefine injection efficiency and

transport factor of a BJT.


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This shows that, to achieve maximum transport factor,

should be minimum. Thiscan be achieved by reducing doping concentration in base and reducing width of base.

Common-base current gain

This is defined as ratio of collector current and emitter

current, when base is common for other two terminals.

This current gain may be ac or dc and can be expressed

as,

dc current gain = We can express

=

+

=

Then = But IC>> ICBO, then = ---(1)ac current gain (out of syllabus topic)

=

= ( ) ICBOis not a function of IE, then

() = And = ---(2)

This shows that for a good transistor, common-base current gain must be close to

unity.

Question:Part A

Define and of a BJT.


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Relationship between common-base current gain, injection efficiency and transport factor

Let M is the multiplication factor in collector-base

junction during the Avalanche breakdown of reverse

biasing. Then M is given by

=

= ---(3) We have = = ---(4) =

=

---(5)

= = Using (5) = Put this to (4)

= =

=

=

---(6)

This shows that current gain can be improved by increasing injection factor andtransport factor.Common-emitter current gain

It is defined as the ratio between collector current and base current when emitter is

common for other two terminals. This also has ac and dc current gain.

It can be expressed by

Question:

Part B

Give the relationship between

basic performance parametersof BJT.


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= ---(7)Relationship between and

We have = Then = ---(8) Base current IB= IrB+ InEICBO---(9)

But = + = Substituting to (9) = +

=

+

(

+

)

= ---(10) (Since = + and = + ) Using = and substituting (8) and (10) =

=

= = ---(11) This shows that, for a good BJT is infinity. In practical it is very high.

and of a BJT can be improved by increasing the emitter injection efficiency and

base transport factor.


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Problem:

The following parameters are given for an npn transistor. InE= -5mA, IpE= -0.01mA,

InC= -4.99mA, IpC= -0.001mA. Determine T, , , , IB, ICand IE.

Solution:

For pnp transistor,

= + Then for npn transistor, = + =

+ . = . For npn transistor,

= + = Then for npn transistor, = +

=

=

+

.

=

.

= + .. = . We have =

Assume M = 1, = . . = . We have

= = .

. = For pnp transistor, IE= IpE+ InEThen for npn, IE= InE+ IpE= -50.01 = -5.01mA For pnp transistor IC= IpC+ ICBO

Then for npn, IC= -(InC+ ICBO)

ICBOis given as IpC= -0.001mA

Then IC=(4.990.001) = +4.991mA


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For pnp transistor IB= IrB+ InEICBO

Then for npn, IB=(IrB+ IpEICBO)

IrB=0.01mA

IB=(0.010.01 + 0.001) =0.019mA

Doping profile of BJT:

For maintaining high injection efficiency and transport

factor, emitter region should be heavily doped and base

region should be lightly doped and narrow width.

For improving switching speed and reduce parasitic

capacitance, collector resistance should be as low as

possible. For that collector doping must be as high as

possible.

If heavily doped collector region is used, under low reverse biasing of collector-base

junction, the depletion layer penetrates more on base region. This reduces the

effective width of base. The complete penetration of depletion layer into the base region is called punch

throughand is similar to breakdown.

During punch through, collector-base voltage loses control over the collector current.

To avoid the punch through, collector doping must be less than that of base. But this

reduces the switching speed and increases power dissipation.

To overcome this situation, collector doping near to base is kept lower than base

doping and collector doping away from base is kept higher than the base doping.

A practical doping profile for pnp BJT is shown below:

Question:

Part A

What are the doping anddimensional requirements of

emitter, base and collector

region of a BJT?


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Energy band diagram of BJT

The energy band diagram of pnp BJT

under isolation, equilibrium, forward active

and saturation region are shown below:

Question:

Part B

Plot the energy band diagram

and potential distribution of pnp

transistor in active region.

(April 2014)


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Potential distribution in pnp BJT under equilibrium and forward active modes:

Equlibrium

Forward active mode


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Question:

Part A

Draw the energy band diagram of npn BJT. (April 2014)


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Minority carrier distribution in pnp BJT

This is helpful to determine terminal currents of BJT in terms of physical dimensions.

The minority carrier distribution of pnp BJT in saturation mode is shown below:

Different components used are:

nE0equilibrium electron concentration in emitter and = pB0equilibrium hole concentration in base and = nC0equilibrium electron concentration in collector and = nEconcentration of electron injected from base to emitter at xE= 0

pEconcentration of hole injected from emitter to base at x = 0pCconcentration of hole injected from collector to base at x = WB

nCconcentration of electron injected from base to collector at x C= 0

We know that the excess carrier in pn junction is = ( ) Using this, = = ---(1)

=

=

---(2)

= = ---(3) = = ---(4) The minority carrier distribution in base region is almost linear, because the current flow in

base region during saturation mode is only due to diffusion of carriers, not recombination.


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Terminal current in terms of physical dimensions:

Consider pnp BJT and assume:

1. Areas of cross-sections of all regions are same.

2. Two junctions are abrupt.

3. Doping concentrations in all regions are uniform.

4.

Minority carrier currents in neutral region are due to

diffusion.

5. Low level injection of carriers.

6. BJT is in steady-state condition.

7. Current flow is only in one-dimension.

8. No generation and recombination in depletion regions.

Apply continuity equation in base region for hole injection,()

=()

---(1)

The solution of (1) is = + ---(2) Apply boundary conditions = ,= =,= Then (2) becomes,

=

+

=

+

---(3)

And = + ---(4) To find unknown constants C1and C2

Multiply (3) by (3) becomes = + ---(5)And (4)(5) becomes

=

(

)

Then = ---(6)Substituting (6) to (3)

Question:

Part B

Derive expressions for IC, IE

and IBof an pnp BJT


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= + =

= + = +

=

---(7)

Substituting (6) and (7) to (2) gives

= + = + =

() +

(

)

()

= (() () ) + ( ) = (() () ) + ( )

= +

---(8) The hole diffusion current in base is = ---(9)


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Substituting (2) to (9) = +

= + = + = ---(10)

At x = 0,

=

= ---(11) Substituting (6) and (7) to (11) gives = =

+

= + =

+

=


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=

= ---(12) At x = WB = Using (10)

=

= = =

+

= + = + =

+


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=

= =

---(13)

Similarly

= ---(14) = ---(15) Then terminal current = +

Using (12) and (14)

= + Substituting (1), (2) and (3) = +

=

+

---(16)

In general = ---(17)


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Where is reverse saturation current of emitter-base junction with collector-base is short circuitedand

=

+

---(18)

is reverse saturation current of collector-base junction with emitter-base is short circuitedand is reverse current gain when emitter-base junction is reverse biased and collector-basejunction is forward biased = ---(19)

The terminal current

=

+

Using (13) and (15) = Substituting (2), (3) and (4)

=

= + + ()

=

---(21)

Where is forward current gain when emitter-base junction is forward biased andcollector-base junction is reverse biased. = + =


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The other terminal current = DC parameters in terms of physical dimensions: Consider pnp BJT in forward active mode. Emitter injection efficiency = + Using (12) and (14)

=

In forward active mode, Then

= If WB


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Then

=

= And =

+

()

Base transportation factor = Using (12) and (13)

=

In forward active mode of BJT, = Then

=

=


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= If WB


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And = Using (24)

= + + + + =

+

+

= + When and

()Problem:1. A Si npn BJT has pB= 1s and pB= 440 cm

2/V-s. Determine WBso that the transport

factor is 0.995 at T = 300K. Assume WB


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= = . = . Then

=

+

. = + . + . = . . = . . = . = . . = . = .

2. Consider the following parameters of npn BJT at 300K:

Emitter Base Collector

Doping 10 cm-

10 cm-

10 cm-

Width 2m 1m 5m

Minoritycarrier

lifetime

0.01s 0.06s 1s

Mobility p= 350 cm /V-s n= 1250 cm /V-s p= 450 cm /V-s

Find , T, and .

Solution:

For npn BJT

=

+

= = = . = ./


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=

=

=

.

=

.

/

= = = = = = =

+.

.

= .

For npn = = = . . = . =

.

= .

Assume M = 1 = = . . = . = = . . =


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Ebers-Moll model of BJT:

This is a large signal model of BJT and is useful to obtain the

characteristics of BJT.

Consider the two diode equivalent circuit of pnp BJT:

We have terminal current equations = () = () In general = () = ()

These equations are referred as Ebers-Moll equations

The Ebers-Moll model of pnp BJT using (3) and (4) is shown below:

Question:

Part BDraw Ebers-Moll model of pnp

BJT and write the Ebers-Mollequations. Explain the term

involved.


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Relationship between IESand ICS: = = Definition of ICBOand IEBO:

ICBO is reverse saturation current in collector-base junction, when emitter is open, i.eIE= 0.

IEBO is reverse saturation current in collector-base junction, when collector is open, i.e

IC= 0.

Relationship between IESand IEBO, ICS and ICBO:

Take = ()Multiply (1) by

= () Take = ()

Add (2) and (3) + = +

= + = + () When IE= 0 = = ()

Where

=

= () Similarly = ()

Question:

Part B

Derive relationship between IESand IEBO

Question:

Part BDerive relationship between ICS

and ICBO


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Problem:

Prove the relations

a) = + b)

=

+ (

+

)

Solutiona) For pnp BJT, we know that = + ()When = , = Then = ()By definition = =i.e

=

(

)

From (1), = Then (3) becomes = = + Hence proved.

b) We have = + ()Take

=

+

(

)

Substitute (1) to (2) = + + = + = + = + ()We know

=

= + = ++ = + Then (3) becomes = + +Hence proved.


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Minority carrier distribution of pnp BJT in different operating modes:

Question:

Part BPlot the minority carrier distribution in pnp BJT in

a) forward active mode b) saturation mode c) cut-off mode e) inverse active mode


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Real BJT:

Consider the following non-idealities for a practical BJT:

1. Carrier recombination in emitter-base junction.

2. Drift in base region.

3. Effects of variation of VCBon terminal currents.

4.

Avalanche multiplication in collector-base junction.

5. Resistance of the base region.

6. Non-ideal structure.

7. Kirk effect.

Effect due to recombination in emitter-base junction

Considering the recombination in emitter-base junction, the emitter current consists that

component also and is given by = ()Where

= is depletion layer width of emitter-base junctionis carrier life time in emitter-base junction Then emitter injection efficiency becomes = + + IRterm reduces , especially is Si and GaAs BJTs at or below room temperatures.

If V

EBand I

Care increased,

becomes negligible and term increases with I

C.

Effect of drift in base region

Uniform doping is not practical in base region. Typically

doping concentration Nd(x) varies exponentially within base

region.

The variation of this doping concentration creates a built-in

electric field from emitter to collector (for pnp BJT).

The electric field adds a drift component to the transport of

hole from emitter to collector.

At equilibrium, the drift and diffusion current balances and current in base In(x) = 0. i.e,+ = Then built-in electric field =

Question:

Part BExplain the effect of non-

uniform doping in base

region of BJT.


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=

=

()

= () () This shows that the built-in electric field is positive directed from emitter to collector.

This electric field helps transport of holes across the base region from emitter to collector

and transit time is reduced.

The reduction in transit time of electron (in npn) or hole (in pnp) is useful for BJT in high

frequency applications.

Effect of bias to collector-base junction (Early effect or base width modulation)

The effective width (WB) of base region is the difference between the total base width(WB0) and the depletion layer width of collector-base junction into the base region. This

is as shown below:

Then = + ()We know that = + Substituting to (1)

= + += + + +


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= + + ()

This shows that the effective width of base region decreases

with increase in reverse-bias on the collector-base junction.

This effect is called base width modulation or Early effect.

Due to Early effect, reverse bias of collector-base junction

increases ICand IE increases.

Increase in VCB, decreases WB and which increase the slope of minority carrier

distribution in base region. Increase in slope results increase in IpEand IpC.

When width of base is reduced, following effects will occur on BJT:

1. Increase IEand IC

2. Decrease IB(due to decrease in recombination in base

region)

3. Increases T

4. Increase and

Question:Part A

What is base width

modulation? (April

2014)

Question:

Part A

What is Early effect? Whatare the effects on IC, IE, IB,

and of BJT?


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Punch through effect:

When VCB increases, depletion layer of collector-base region penetrates more into the

base region and the effective width of base decreases and become zero at a collector-base

reverse bias voltage called punch-through voltage (VPT).

Usually Avalanche breakdown occur only after this.

Using (2)

= + +

= + + = + + =

+

+

+ = +

Typically , then = +

Question:Part B

What is meant by punch

through in a BJT? How is itavoided?


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Avalanche multiplication in collector-base junction

Avalanche multiplication takes place in the reverse biased collector-base depletion

region, when VCBis very high.

Then of BJT increases causes increase in ICfor a given IE.

The current entering collector-base depletion layer is IpC, current reaching collector is IC.

Also IC= IpC+ ICBO, then multiplication factor = + (1) Avalanche multiplication factor is also given by = ()

Where n lies between 2 and 7

For low VCB, M is unity.


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Problem:

Solution:

We can write effective width of npn BJT collector-base junction

= + +

=

+

+

+ = + = = . . = . = + =

.

..

+

.

= .. = .Resistance of base region and emitter crowding

In real structure of BJT base region has large in area comparing to emitter and the

resistance of base is distributed over this region. This is shown below:

Question:

Part B

A Si npn bipolar transistor has NdC= 1018

cm-3, NaB= 10

15cm

-3and WB=

1m. Determine the punch through voltage. (April 2014)


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The effective resistance of base depends on the doping

concentration of base and its geometry. So this resistance is

also called base spreading resistance rB.

Due this resistance, the applied voltage is modified as

VEB VEB- IBrBand VCB VCB- IBrB

Then the carrier flow between emitter and collector is not through center and is through

the peripheral sides of emitter. This is called emitter crowding.

Static V-I characteristics of BJT

There are three configurations for characteristics of BJT. They are:

1. Common-Base (CB) configuration

Base is common to both input and output.

2. Common-Emitter (CE) configuration

Emitter is common to both input and output

3.

Common-Collector (CC) configuration Collector is common to both input and output

CB configuration:

The circuit arrangement of pnp BJT in CB configuration is shown below:

Here the input current is IE(+ve), input voltage is VEB(+ve), output current is IC (-ve) and

output voltage is VCB (-ve).

Question:

Part AWhat is meant by emitter

crowding?


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Input characteristics of CB configuration

It is the plot of input current IEas a function of input voltage

VEBwith output voltage VCBheld constant.

By Ebers-Moll equation,

= When collector-base region is under reverse biased, VCB< 0V = + Then the plot of input characteristics under different VCB is

shown below:

The shape of this characteristic is similar to pn junction diode, but increasing reverse bias

VCBshifts the characteristics to left side.

When VCBincreases, reduce base width cause an increase in IE. i.e is the reason for shift

of the curve to left.

This shift is also the consequence of Early effect.

Output characteristics of CB configuration

It is the plot of output current ICas a function of output voltage VCBwith input current IEheld constant.

Consider the equation = +

= + () When IE= 0, and VCB 0(collector-base reverse bias voltage),

Question:

Part B

Plot the input and output

characteristics of a pnptransistor in common-base

configuration and explain?Marks different operating

regions.Question:

Part A

Draw the input

characteristics of a

pnp transistor in

common baseconfiguration.

(October 2014)


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= ()ICis constant.

When IE> 0, and VCB 0,

=

(

)

ICremains constant, if IEis constant. When VCB> 0 (collector-base junction forward biased), ICdecreases due to injection of

holes from collector to base. For a finite VCB, collector current becomes zero and using

(1) = + = =

= = = () Then the output characteristics of CB configuration is as shown below:

For IE = 0, VEB should be 0 (emitter-base reverse bias) and VCB 0 (collector-base

reverse bias), that region is labeled as cutoff region. Here IC 0, for IE= -ICEO. For IE> 0, VEB> 0 (emitter-base forward bias) and VCB> 0 (collector-base forward bias),

that region is labeled as saturation region. Here IClinearly increases with increase in IE.

For IE> 0, VEB> 0 (emitter-base forward bias) and VCB 0 (collector-base reverse bias),

that region is labeled as active region. Here IC= - IE.


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Solution:

For npn BJT in CB configuration, input voltage VEB(-ve), input current IE(-ve), output voltage

VCB(+ve).

Input characteristics is plot of IEas a function of VEBby keeping VCBconstant.

Question:

Part A

Draw the input characteristics of an npn transistor in

common base configuration. (April 2014)


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CE configuration:

The circuit arrangement of pnp BJT in CE

configuration is shown below:

Here the input current IB(-ve), input voltage VBE(-ve), output current IC(-ve) and output

voltage VCE(-ve).

Input characteristics of CE configuration

It is the plot of input current IBas a function of input voltage VBEwith output voltage VCEheld constant.

Consider Ebers-Moll equations, = = = = +

=

+

+

(

)

In this configuration VCE= VCB+ VBE,then VCB= VCEVBE

If VCE VBE , VCB 0, and collector-base junction becomes reverse biased. Then (1)

becomes = + +

Question:

Part B

Explain the

characteristics of

transistor in CE

configuration. (April

2014)


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Consider the equation = + +When IB= 0, i.e.

=

+

= Where ICEO is current between emitter and collector whenbase is open. It is (1+) times more than ICBO. With reverse

biased collector-base junction, electron drifts from collector to

base and it accumulates there produces a small forward bias

on the emitter-base junction cause an injection of holes from emitter to base. This results

the current ICEO

The plot of output characteristics for CE configuration is shown below:

For IB= 0, VBE 0, therefore VEB 0 (emitter-base junction reverse biased) and VCE 0,

VCB= VCE- VBE

VCB= VCE+ VEB 0 (collector-base junction reverse biased).

This region is labeled as cutoff region. Here |IC| = ICEO.

For IB< 0, VBE< 0, therefore VEB> 0 (emitter-base junction forward biased) and if VCE

varies from 0 to -VBE, VCBwill be VBEto 0 (collector-base junction forward biased). Thisregion is labeled as saturation region. Here ICincreases linearly with increase in VCE.

For IB < 0, VBE< 0, therefore VEB> 0 (emitter-base junction forward biased) and if VCE> The effect of Avalanche breakdown in output characteristics of CE configuration is

shown below:

Question:

Part B

Explain Early effect in CE

configuration. What is Earlyvoltage?


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Field Effect Transistors (FET):

These transistors are work on the principle of field effect. It

uses the transverse electric field to control longitudinal

current flow between two terminals.

The current flow in these devices is only due the majority

carriers only. So these are unipolar devices.

Due to the absence of minority carriers, there is no generation/recombination process

involved in the conduction.

FETs are less temperature dependence and more immune to radiation.

The fabrication of FETs is simpler than BJTs and they

occupy less area only.

Due to the high noise immune, they are applicable as high

frequency amplifiers in satellite communication. They are

also suitable for operational amplifiers, instrumentation

amplifiers etc. because of the high input resistance. Due thesmall occupancy are, they are suitable for constructing microprocessors, memory chips

etc.

Different types of FETs are:

1. Junction FET (JFET):

2. Metal Oxide Semiconductor FET (MOSFET): Field

effect is obtained by metal-oxide semiconductor

interface.

Junction FET (JFET):

In this FET, field effect is obtained by the pn junction.

There are two types of JFET:

1. n-channel JFET

2. p-channel JFET

A simplified structure of a n-channel JFET is shown below:

Question:

Part A

What is meant by field effect

transistor?

Question:

Part A1. What are the advantages of

FETs over BJTs?

2. List the applications of FETs.

Question:

Part AHow are FETs classified?

Question:

Part AExplain the fabrication of JFET.


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It consists of a lightly doped n-region sandwiched between two p+ regions. The middle n

region is called channel of the JFET and the p+ regions form gate. (In case of p-channel

JFET, p-channel and n+ gates are there.)

One end of the channel is designated as source (S) and other end as drain (D). These are

interchangeable terminals. For n-channel JFET, terminal to which higher potential is

applied acts as drain.

The drain collects the charge carriers emitted from the source through the channel.

The gate (G) terminal controls the flow of current through the channel.

The symbol of FET is:

The real structure of single gate n-channel JFET is shown below:


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Principle of operation of JFET:

Consider the simplified schematic structure of dual gate n-

channel JFET as shown below:

Let the channel thickness is 2a, channel width Z, channel length L, W 0depletion layer

width of gate to channel junction on both side under thermal equilibrium and Nddoping

concentration of channel.

The resistance of the channel with no bias (VGS = 0,

VDS= 0) or under equilibrium is given by = = ()Conductivity of the channel

=

(

)

Area of cross section of the channel = ()Substituting (3) and (2) into (1) = = ()or conductance of the channel =

=

()

Depletion layer width of the channel at equilibrium is = ()Where V0is built-in potential of gate to channel junction.

The resistance of the channel can be varied by varying the gate voltage. So the gate

terminal acts as a control terminal.

Question:

Part B

Explain the working ofan n-channel JFET.

(October 2014)

Question:

Part BDerive expression for

equilibrium conductance of the

channel of JFET.


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When reverse bias on the gate increase, depletion layer extends more into the channel.

Then effective channel thickness and channel cross section area reduces, cause decrease

in channel conductance.

Changing conductance of channel by gate voltage is called conductance modulation.

When a drain to source voltage VDS is applied, the drift current through the channel ID

and is governed by Ohms law. i.e = . The channel resistance R can be controlled by gate voltage VGS. It also changes according

to VDS.

Drain characteristics of JFET:

It is the plot of drain current ID as a function of drain to

source voltage VDS keeping gate to source voltage VGS

constant.

Case 1: If VGS= 0, VDS= 0, R = R0and ID= 0

Case 2:If VGS= 0, 0 < VDS< V0, for small VDSchange in R is negligible, so it is almost

close to R0. Then ID increase linearly with increase in VDS. This portion of drain

characteristics is called linear region or ohmic region. This is shown below:

Question:

Part B

Draw and explain the

drain characteristics ofan n-channel JFET.

(April 2014)Hint: Answer each case and

draw drain characteristics.

Dont answerpinch-off voltage

derivation.


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= =

=

= ()This shows that the pinch-off voltage is unique for a given JFET and is depends on the

channel doping and channel width. If doping concentration or channel width increases

pinch-off voltage increases.

At pinch-off, IDbecomes constant and is denoted as ID(sat)as shown below:

Case 5: If VGS= 0, VDS> VD(sat), more portion of channel width becomes pinch-off and

current flow in longitudinal direction and remain constant. This is shown below:

Case 6: If VGS = 0, VDS is higher value, the reverse biased gate channel junction

breakdown due to Avalanche multiplication. Then IDincreases uncontrollable.

The drain characteristics for VGS= 0 is shown below:


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Case 7: If VGS < 0 (increases reverse bias), increase depletion width and channel

resistance. This reduces the slope of the characteristics in ohmic region. This also reduces

VD(sat) and ID(sat). With increase in VDS and VGS (reverse bias), Avalanche breakdown

occurs also decrease. Then the complete drain characteristics of JFET is shown below:

From this characteristics, an important parameter for JFET is dynamic drain resistance rD

and is given by =

(

)

The value of VGSat which channel gets completely depleted is called cut-off voltage orthreshold voltage Vthof JFET.


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Transfer characteristics of JFET:

It is the plot of the drain current ID as a function of gate to source voltage VGSby

keeping VDSas constant.

At a constant VDS, if reverse bias between gate and source is increase, ID will

decrease as shown below:

The drain current is maximum when VGS= 0 due to minimum channel resistance and

it reduces to zero when VGS= VGS(cut-off), where VGS(cut-off) is given by

() = The slope of the transfer characteristics gives a parameter called transconductance gmand is given by = ()Static I-V characteristics, current equation and device parameters:

To derive static I-V characteristics, consider the following assumptions:

1. Mobility of channel remains constant.

2.

The gate and channel are uniformly doped.3. The length of the channel L is large compared to its thickness 2a.

4. Applied VDS VD(sat)


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Consider the cross sectional view of JFET with direction current and variation of

depletion layer along the channel.

The current through the channel is given by

=

(

)

Where A(x) is area of cross section of the channel at distance x, is the channel

conductivity and is the electric field at x in the channel. Area of cross section = ()Depletion width in the channel along x-axis,

= + +() Where

+

+

(

)

represents the reverse bias between channel and gate at

distance x. VGSis alwaysve, otherwise input resistance of JFET becomes low. Then

= + () Then

= + () () The conductivity of the channel is

= () Electric field = () ()


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Substituting (3), (4) and (5) into (1),

=

+ ()

()

= = + () () = + () ()

Integrating both sides,

= + () () = + ()

()

= + ()

()= + () ()

= + () ()

=

+

(

)

(

)

= + ()

()(Neglecting W0in G0)


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= () + ()

= () +

(

)

= + = +

+

=

+

(

)

This is the current equation for JFET.

Threshold voltage, Vth:

It is the voltage applied to gate to completely deplete the channel or reduce the channel

thickness to zero. This results ID= 0.

It is given by = ()Drain current at saturation, ID(sat):

It is the drain current at VDS= VD(sat), and is given by

() = + +

()Where

=

(

) +

Channel conductance, gD:

It can define as = = () It is given by

Question:

Part A

Express the equation for a) Vth)b) ID(sat)c) Channel conductance

d) Transconductance.


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= + ()

In ohmic region, 0< VDS


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Problem:

An n-channel Si JFET at 300K has width Z = 1mm, channel thickness on one side a = 1m,

channel length L = 25m, channel doping Nd = 1016

cm-3

and the gate doping is 1019

cm-3

.

Determine: a) contact potential b) pinch-off voltage c) current at VGS = - 2 V, VDS= 3V and

d) saturation current at VGS = -2V using theoretical and approximate expressions. Take n =

1100cm2/V-s.

Solution:

a) = = . . = .b) = = ... = .c) Gate to channel voltage VGC= VDS+ V0- VGS= 3 + 0.877(-2) = 5.877V

And VGC< VP, Then transistor is in saturation region and

= + = = .

= . = .

. .

.

. ()

.

= .d) () = + + = . .. .+ . .+. = .Approximate value

(

) =

+


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=

+

= . .. .+ . ..

= .() = . + . = .

Real JFET:

The characteristics of real JFET are:

1. Channel length modulation: Ideally drain current is

constant after pinch-off, but really it increases slightly

with VDSafter pinch-off.

The effective length of channel decreases after pinch-

off, then the channel conductance G0 increases. This

shows that conductance of channel is modulated by the variation in effective length

by VDS. This is called channel length modulation. Due to this ID increases with

increase in VDSafter pinch-off.

2. High field effects: The electric field along the channel is very high, if the channel is

short. The velocity of electron at high electric field has saturation, then mobility of

electron decreases with increase in electric field. Then there is a reduction in

conductance of the channel and IDfor a given VDS.

3. Breakdown: In JFET, gate channel junction is always reverse biased. Then for large

values of VDSmay cause Avalanche breakdown of the junction. For more ve values

of VGS, the breakdown occurs at the smaller values of VDS.

4. Temperature effects: With increase in temperature the

mobility of carriers decreases due to increase in

scattering by lattice vibration. This leads to reduction in

IDwith rise in temperature.

Question:Part A

What is meant by channel

length modulation in JFET?

Question:

Part A

What is the effect of increase in

temperature on JFET drain

current?


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Metal Oxide Semiconductor (MOS) Systems:

MOS capacitors and MOSFET are charge coupled devices.

MOS capacitor is a two terminal device and may be considered as a MOS diode.

MOSFET is a FET, which make use of MOS capacitor for modulate channel

conductance.

MOSFET are superior to BJTs due to many factors, some are: high scale of integration,

high gain-bandwidth product. MOSFET are always considered for applications in high

speed digital circuits, high density ICs etc.

MOS Capacitors:

A two terminal metal oxide semiconductor system is used as a MOS capacitor (or MOS

diode).

The structure of a metal (Al) oxide (SiO2) semiconductor

(p-type Si) capacitor is shown below:

An ideal MOS capacitor have:

1. Equal work function for metal and semiconductor

2.

Oxide acts as a perfect insulator and no trapped charges, no defects and no interface

states.

The capacitance per unit area of MOS capacitor is given by = Where is permittivity of oxide and toxis thickness of oxide.

Question:

Part ADraw the simplified structure of

MOS capacitor.


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Energy band diagram of MOS capacitor:

To draw the energy band diagram of MOS capacitor consider the following tips:

1. At equilibrium Fermi level is a common horizontal line

2. When biasing voltage is applied, Fermi level on the semiconductor side moves up or

down relative to that of semiconductor.

3.

The conduction band and valence band of oxide bends in the direction of electric

field.

4. With any bias, the relative positions of EC, EV, and Eiremain unchanged with respect

to oxide conduction band edge at the interface.

The equilibrium energy band diagram of a MOS capacitor is shown below:

In MOS capacitor, there is no current flow from metal to semiconductor or

semiconductor to metal under any bias.

Case 1 (VG< 0 or accumulation):

When a negative voltage is applied to the metal with respect to semiconductor (VG< 0),

+ve charges are induced on the semiconductor.

The induced charges accumulate near the oxide-semiconductor interface. Then there is aincrease in hole concentration near the interface.

Question:

Part B

Draw the energy band diagramof MOS capacitor under

a) Equlibrium b) Accumulationc) Depeltion d) Inversione) Strong Inversion


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The change in carrier concentration near the interface causes a bending of energy band at

the interface. Then the energy band diagram of MOS capacitor under VG < 0 (called

accumulation) is as shown below:

The semiconductor outside the accumulation region remains neutral. When VGincreases

vely, the Fermi-level on the semiconductor side shifts downward by qVG.

Under this condition, the effective capacitance of MOS capacitor is the series

combination of oxide capacitance and capacitance of accumulation layer.

The accumulation layer is very thin, so its capacitance is very high, then the effective

capacitance is same as Cox.

Case 2 (VG> 0, or depletion):

When a small +ve voltage is applied to the metal with respect to semiconductor (VG> 0),-ve charges are introduced in p-type semiconductor,

Theve charges moves towards metal-semiconductor interface and they recombine with

holes. Then depletion layer formed near the interface.

The energy band diagram for this bias voltage is shown below:


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Fermi-level of semiconductor due to the bias shifts upward by qVG.

The bending of energy band near the interface in the depletion region. Then the effective

capacitance of the MOS capacitor is the series combination of oxide capacitance Coxand

the depletion layer capacitance CD. It is given by

= + (All capacitance are in F/cm2) The charge per unit area in semiconductor in the depletion layer is given by =

Where W is width of depletion layer and is given by

= And

is called surface potential and is given by

= Where Eib is intrinsic level in the bulk semiconductor and E is is intrinsic level at the

surface of interface.

Case 3 (VG>> 0 or inversion) :

When VGis increased to high value, Fermi-level on the semiconductor move upside and

band bends downside. Then the Fermi-level at the interface lies above the intrinsic level.

This result inversion of interface surface and is called inversion.

The inversion of surface is due to the attraction of electrons towards the surface, and the

concentration of electrons near the interface becomes more than hole. Then the thin region in which electron concentration exceeds hole concentration is called

inversion layer. This is shown below:


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Once inversion occurs, further increase in VG cause only increase in inversion layer

charge.

The thickness of inversion layer is very small compared to W.

The total charge in the semiconductor under this condition is given by

= += Where is charge per unit area of electrons in the inversion layer, Wm maximumwidth of depletion layer and QDm is maximum value of the charge per unit area of

depletion layer.

Further increase in VG cause the intrinsic level at the interface surface goes below the

Fermi-level by an amount equal to or above of the Fermi-level at the bulk semiconductor.

Then electron concentration at the interface surface become equal to hole concentration

in the bulk. This is called strong inversion. This is shown below:

Fermi-potential is defined by = ()

It depends on the semiconductor doping concentration.

Surface potential = Under strong inversion =

or = ()


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From (2), = Substituting into (3) = + ()From (1),

=

Then (4) becomes = + = + = = () This shows that under strong inversion, surface potential is twice of Fermi potential. And

highly concentration of electrons is present in the surface.

Relation of charge densities:

We have carrier concentration under equilibrium,

= = Here hole concentration =

= ()Where Fermi potential

=

(

)

Here electron concentration = = () The electron concentration in the surface of p-type semiconductor is given by =

But

= (

)

(

)

= ( )+( )Then = + = = ()


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Under thermal equilibrium, = then =

Increasing VG causes increase in

and increase in

electron concentration. When = , = . Atthis point inversion starts and when > , electronconcentration in the surface exceeds ni (i.e. ns> ni). Thensurface semiconductor inverted.

At strong inversion = , = =

i.e minority carrier concentration at the interface is same as majority carrier concentration

in the bulk semiconductor.

After strong inversion, a small increase in VGcauses only a large increase in nSonly, not

in W.

C-V characteristics of MOS capacitor:

In MOS device, capacitance varies according to applied bias voltage V G. When a voltage

VGis applied to gate (Metal), a part of it drops in oxide and reminder in semiconductor.

Then = + ()Where Voxis voltage across oxide.

By definition of oxide capacitance,

= ()We have = Then (1) becomes = + ()

When VGchanges, Qsand Schanges, then differentiating (3) w.r.t VG

=

+

= + ()Let capacitance per unit area of the MOS device is defined as = = () ()

Question:

Part AWhat is the value of surface

potential of a MOS capacitor

under a) at the inversion b)strong inversion?


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Let semiconductor capacitance is defined as = ()Substituting (5) and (6), (4) becomes

= + = + = + =

+

()

This shows that oxide capacitance and semiconductor capacitance are in series. Cox isalways constant and Csis dependent on bias.

At accumulation (VG< 0), C = CGand at depletion (0 < VG

< Vth), CS= CD. CDdecreases with increase in VGdue to

increase in depletion width.

At strong inversion, depletion width remains constant and

CSwill constant.

The equivalent capacitance of MOS devices is shown

below:

Question:

Part B

Draw and explain the

C-V characteristics of

an ideal MOS

capacitor. (October

2014)


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The C-V characteristics of MOS device is shown below:

If capacitance is measured at high frequency signal, the inversion layer didnt respondwith the gate voltage. The Cs effect is negligible and CD is effective. When VG < 0

(accumulation), C = Cox and is constant. When VG > 0 (depletion), CD decreases and

C CDand varies with VG. When VG>> 0 (inversion and strong inversion), CDgoes to

minimum and constant, since depletion width is also constant. Then C = Cmin.

At low frequency, depletion layer width is almost constant and CDis negligible. The net

capacitance is decided by inversion layer capacitance CS and Cox. When VG < 0

(accumulation), C = Cox and is constant. When VG > 0 (depletion), Cs decreases and

C CSand varies with VG. When VG>> 0 (inversion and strong inversion), CSgoes to

high and is more than Cox, then C = Cox.

Threshold voltage of MOS capacitor:

It is the voltage required to introduce strong inversion in

the semiconductor.

It is VG at strong inversion. Then = +=

+

At inversion, = = =

Question:

Part BDefine threshold voltage of

ideal MOS capacitor.


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= Then

= = ()

Substituting (2) to (1)

=

+

(

)

This shows that threshold voltage of MOS devices is inversely proportional to oxidecapacitance.

Problems:

1. For a MOS capacitor formed on p-type Si substrate doped with Na = 5x1016

cm-3

,

determine the surface potential required to make the surface: a) intrinsic b) at strong

inversion.

Solution:

a) At inversion (intrinsic),

=

=

=

.

.

= .b) At strong inversion = = . = .2. A Si MOS structure at 300K is characterized by Na= 4x10

14cm

-3, tox= 0.1m. Oxide is

idea. The metal is brought to a potential of +1V with respect to semiconductor rox = 3.9.

a) Does inversion occur? b) Calculate voltage across oxide.

Solution:

If VG> Vthinversion occurs. Given that VG= 1V.

We have

= + = = . . = .


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= = = . .. = . /

=

... ..

+

.

= .a) Given VG> Vth, then strong inversion occurs.b) At strong inversion = = . = . = + = = . = .Real MOS systems:

Real MOS devices have:

1.

Work function difference of metal and semiconductor2. Oxide and interface charges

3. Change in Vthdue to the different work functions.

Typically work function q of metal (Al) is less thanthat of semiconductor. Therefore at equilibrium, there is a

bend in conduction bands of interface at equilibrium. So to

obtain flat band a negative voltage must be applied at VG

and is referred as flat band voltage VFB.

There will be lot of charges in oxide layer and will affect oxide-semiconductor interface.

Different charges are:

1.

Ionic charges Presence of Alkali ions like Na+shifts

the threshold voltage.

2. Fixed oxide charges These charges located in oxide

as a sheet of +ve charge near Si-SiO2 interface.

3. Interface charges These charges present in Si-SiO2

interface due to the sudden termination of

semiconductor at the interface.

4. Trapped charges Oxide may contain trapped charges within the defects present in

the oxide.

Due to the flat band voltage, the modified threshold voltage is given by

Question:

Part BWhat are the non-idealities in a

real MOS capacitor? How dothey change flat band voltageand threshold voltage?

Question:

Part AWhat is meant by flat band

voltage?

Question:

Part AWhat are the different charges

present in the oxide? How do

they affect the threshold ofMOS system?

109.SD Module 3 Notes

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