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Lecture 7. AMBA
Prof. Taeweon SuhComputer Science Education
Korea University
COMP427 Embedded Systems
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AMBA
• Advanced Microcontroller us Architecture !n"chip #us protocol from A$M
• !n"chip interconnect speci%cation for the connectionand mana&ement of functional #loc's includin&processor and peripheral devices
(ntroduced in )**+
AMA is a re&istered trademar' of A$M,imited.
AMA is an open standard
2-i'ipedia
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AMBA istory
• AMBA AS AP
• AMBA 2 )***/ A0
• widely used on A$M12 A$M* and A$M Corte3"M #aseddesi&ns
AS AP4 or AP/
3-i'ipedia
• AMBA ! 4556/
A7(6 or A7( v).5/• widely used on A$M Corte3"A
processors includin& Corte3"A*
A0",ite v).5 AP6 v).5 AT v).5
• AMBA 4 45)5/ ACE
• widely used on the latest A$MCorte3"A processors includin&Corte3"A1 and Corte3"A)8
ACE",ite
A7(9 A7(9",ite A7("Stream v).5 AT v).) AP9 v4.5
ACE: A7( Coherency E3tensions
A7(: Advanced e7tensi#le (nterfaceA0: Advanced 0i&h"performance us
AS: Advanced System us
AP: Advanced Peripheral us
AT: Advanced Trace us
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ASB
4AMA Speci%cation ;4.5
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ASB
5
ard"are#evice $
ard"are#evice %
ard"are#evice 2
ard"are#evice !
ard"are#evice 4
ard"are#evice &
ASB
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AB
6AMA Speci%cation ;4.5
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AB "it' ! Masters and 4S(aves
7AMA Speci%cation ;4.5
<0= indicates A0 si&nals
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AB Basic )rans*er E+am,(e "it'-ait
8AMA Speci%cation ;4.5
0$EA>? Source: Slave
-rite data
$ead data
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AB Burst )rans*er E+am,(e
9AMA Speci%cation ;4.5
0$EA>? Source: Slave
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A# S,(it )ransaction
10AMA Speci%cation ;4.5
• (f slave decides thatit may ta'e a num#erof cycles to o#tainand provide data2 it&ives a SP,(T transfer
response
• Ar#iter &rants use ofthe #us to othermasters
0$ESP: Transfer response fro slave !KA?2 E$$!$2 $ET$?2 and SP,(T/
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APB -rite/ead
11AMA Speci%cation ;4.5
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A01 v%.$
• AMA A7( protocol is tar&eted at hi&h"performance2 hi&h"fre@uency system desi&ns
• A7( 'ey features
Separate addresscontrol and data phases Support for unali&ned data transfers usin& #yte stro#es
Separate read and write data channels to ena#le low"cost >irect Memory Access >MA/
A#ility to issue multiple outstandin& addresses
!ut"of"order transaction completion
Easy addition of re&ister sta&es to provide timin&closure
12AMA A7( Speci%cation ;).5
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& 1nde,endent C'anne(s
• /ead address c'anne( and -rite address c'anne( ;aria#le len&th #urst: ) B )+ data transfers
urst with a transfer sie of D B )549 #its ) B )4D/
• /ead data c'anne(
Convey data and any read response info. >ata #us can #e D2 )+2 642 +92 )4D2 48+2 8)42 or )549 #its
• -rite data c'anne(
>ata #us can #e D2 )+2 642 +92 )4D2 48+2 8)42 or )549 #its
• -rite res,onse c'anne( -rite response info.
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A01 /ead O,eration
14AMA A7( Speci%cation ;).5
/eadAddressC'anne(
/ead#ataC'anne(
$$EA>?: rom master2 indicate that master can accept the read data and response info.
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A01 -rite O,eration
15AMA A7( Speci%cation ;).5
-riteAddressC'anne(-rite#ataC'anne(
-rite/es,onseC'anne(
-;A,(> Source: Master
-$EA>? Source: Slave
;A,(> Source: Slave
$EA>? Source: Master
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Outo*order Com,(etion
• A7( &ives an (> ta& to every transaction Transactions with the same (> are completed in order
Transactions with diFerent (>s can #e completed out oforder
16AMA A7( Speci%cation ;).5
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1# Si3na(s
17AMA A7( Speci%cation ;).5
-riteAddressC'anne(
-rite#ataC'anne(
-rite/es,onseC'anne(
/eadAddress
C'anne(
/ead#ataC'anne(
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Outo*order Com,(etion
• !ut"of"order transactions can improve system
performance in 4 ways ast"respondin& slaves respond in advance of earlier
transactions with slower slaves
Comple3 slaves can return data out of order• A data item for a later access mi&ht #e availa#le #efore the data
for an earlier access is availa#le
• (f a master re@uires that transactions are completedin the same order that they are issued2 they must allhave the same (> ta&
• (t is not a re@uired feature Simple masters and slaves can process one transaction at
a time in the order they are issued
18AMA A7( Speci%cation ;).5
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Addition o* /e3ister S(ices
• A7( ena#les the insertion of a re&ister slice in
any channel at the cost of an additional cycle
latency
Trade"oF #etween latency and ma3imum fre@uency
• (t can #e advanta&eous to use
>irect and fast connection #etween a processor and
hi&h"performance memory
Simple re&ister slices to isolate a lon&er path to less
performance"critical peripherals
19AMA A7( Speci%cation ;).5
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Bacu,S(ides
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A Com,uter System
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CPU
5ort'Brid3e
Sout'Brid3e
Main
Memory6##/2
8SB 68rontSide Bus
#M16#irect Media 18
ard dis
USB
PC1e card
1O devices
9ra,'ics card
A ) i ( 1O S t S ' ti
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A )y,ica( 1O System Sc'ematic6Sim,(i:ed
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Memory Bus; 1O bus
CPU Core
Cac'e
MainMemory
#is
1OContro((er
9ra,'icsCard 5et"or
1nterru,ts
#is
1OContro((er
1OContro((er
MemoryContro((er
bus
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1O 1nterconnection
• A bus is a shared communication lin' A sin&le set of wires used to connect multiple components
• Composed of address #us2 data #us2 and control #us readwrite/
Advanta&es
• ;ersatile G new devices can #e added easily and can #e moved#etween computer systems that use the same #us standard
• ,ow cost G a sin&le set of wires is shared in multiple ways
>isadvanta&es
• Communication #ottlenec' G #us band"idt' limits the ma3imum (!t'rou3',ut
• The ma3imum #us speed is lar&ely limited #y
The (en3t' of the #us
The number of devices on the #us
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1O 1nterconnection 6Cont
• (! devices and interconnection lar&ely contri#ute tothe performance of computer system
• Traditionally2 parallel shared wires had have/ #eenused to connect (! devices
• As the cloc' fre@uency increases for communicatin&
with (! devices2 parallel shared wires suFer fromcloc' s'ew and interference amon& wires
• (ndustry transitioned from parallel shared #uses tohi&h"speed serial point"to"point interconnections
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)y,es o* Buses
• Processormemory bus
ront Side us S/2 proprietary #us• $eplaced #y HP( Huic'Path (nterconnect/ in (ntel
• $eplaced #y 0ypertransport in AM>
Short and hi&h speed
Matched to the memory system to ma3imie thememory"processor #andwidth
!ptimied for cache #loc' transfers
• Bac,(ane 6bacbone bus (ndustry standard
• e.&.2 PC(e3press
Allow processor2 memory and (! devices tocoe3ist on a sin&le #us
Used as an intermediary #us connectin& (!#usses to the processor"memory #us
• 1O bus (ndustry standard
• e.&.2 SATA2 US2 irewire
Usually is len&thy and slower
Ieeds to accommodate a wide ran&e of (!devices
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CPU
5ort'Brid3e
Sout'Brid3e
MainMemor
y6##/2
8SB
68rontSide Bus
#M1
6#irect Media 18
ard dis
USB
9ra,'ics card
Processormemorybus Bac,(ane bus
1O bus
o" #oes CPU Access 1O
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Memory S,ace
o" #oes CPU Access 1O#evices<
• All the (! devices have re&isters
implemented2 so softwarepro&rammers can use them to controlthe devices Then2 for pro&rammin&2 where and how
to write to or read fromJ
There are 4 ways to access (! devices• Memory"mapped (!
• (!"mapped (!
• Memoryma,,ed 1O (! device is mapped to a memory space
CPU &enerates a memory transaction toaccess (! device
To access (! device• (n M(PS2 use lw or sw instructions
• (n 3D+2 use mov instruction
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535
53
9L")/
Main Memory6%9B
536
)L")/
1O device
1O device
1O device
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o" CPU Accesses 1O #evices<
• 1Oma,,ed 1O
(! devices are mapped to (! space CPU &enerates (! transaction to access
(! device
To access (! device• (n 3D+2 there are in and out instructions.
• (n 3D+2 (! space is +9K
• To diFerentiate memory space and (!space2 there should #e hardwaresupport (SA support
• (n 3D+2 mov instruction for memory transactionand in,out instruction for (! transaction
Physical pin from processor indicatin& thetransaction type memory or (!/
• or e3ample2 the pin is driven to <)= formemory transaction or <5= for (! transaction
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535
1O S,ace
6=4KB in +>=
53
+9K")/
1O device
1O device
1O device
o" 1O Communicates "it'
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o" 1O Communicates "it'CPU<
• Po((in3
CPU periodically chec's the status of (! devices to determineits need for service
• CPU is totally in control
• Can waste a lot of CPU time due to speed diFerences
• 1nterru,t
(! device issues an interrupt to indicate that it needsattention
An (! interrupt is asynchronous wrt with respect to/instruction e3ecution
• (t is not associated with any instruction2 so doesnt prevent anyinstruction from completin&
• ?ou can pic' your own convenient point in the pipeline to handle theinterrupt
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#MA 6#irect Memory Access
• Typically2 movin& data from one place to another involve CPU
instructions ,oad lw/ from a location e.&. memory in an (! device/
Store sw/ to another location e.&. main memory/
Movin& a lar&e chun' of data with CPU instructions could ta'e a lar&e fractionof CPU time
• >MA has the a#ility to transfer lar&e #loc's of data direct(y tofromthe memory "it'out invo(vin3 t'e ,rocessor
). The processor initiates the >MA transfer #y supplyin& source and destinationaddresses2 the num#er of #ytes to transfer
4. The >MA controller mana&es the entire transfer possi#ly thousand of #ytesin len&th/2 ar#itratin& for the #us
6. -hen the >MA transfer is complete2 the >MA controller interrupts theprocessor to inform that the transfer is complete
• There may #e multiple >MA devices in one system
Processor and >MA controllers contend for #us cycles and for memory
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