The versatile hardware accelerator framework for sparse vector calculations Michał Karwatowski 1,2,...
15
The versatile hardware accelerator framework for sparse vector calculations Michał Karwatowski 1,2 , Kazimierz Wiatr 12 1 AGH University of Science and Technology, al. Mickiewicza 30, 30-059 Kraków, 2 ACK Cyfronet AGH, ul. Nawojki 11, 30-950 Kraków RUC 17-18.09.2015 Kraków
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Transcript of The versatile hardware accelerator framework for sparse vector calculations Michał Karwatowski 1,2,...
The versatile hardware accelerator framework for sparse vector calculations
Michał Karwatowski1,2, Kazimierz Wiatr12
1AGH University of Science and Technology, al. Mickiewicza 30, 30-059 Kraków,2ACK Cyfronet AGH, ul. Nawojki 11, 30-950 Kraków
RUC 17-18.09.2015 Kraków
2Agenda
Text processing
Sparse data
Hardware architecture
Results
Future work
3Text similarity analysis
Vector Space Model
Term Frequency – Inverse Document Frequency
Cosine similarity
4Sparse data
V00001001101000110100111001111
V1000000100011011110101100
V20010011010011100
V30001001000110100011001111001101010111110
V400110100010101111001
V50000000100100011010001010110011110001001101010111100110111101111
V6000100110101100111001111
V700100011010010001100110111101111
5Text comparison
6Top level hardware architecture
7Hardware processing system
8Cascaded stream splitter
9Processing channel
10ZedBoard
Dual-core ARM Cortex-A9 667 MHz
512 MB RAM connected to PS
FPGA XC7Z02085k logic cells
140 block RAMs
11VC707
Intel Core i7 950 3066 MHz
12 GB RAM
FPGA XC7VX485T485k logic cells
1030 block RAMs
PCIe Gen2x8
12Resource utilization – 8 channels
13Power usage
14Work in progress
32 internal channels in Zynq
192 internal channels in Virtex
Database in DDR3 memory
OpenCL
15Questions
?
