Maciej Goaszewski Tutor: Tadeusz Sondej, PhD Design and implementationof softcore dual processor systemon single chip FPGAMilitary Universityof TechnologyFaculty of ElectronicsInstitute of Telecommunication

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Multiprocessor SoCs in FPGAExamples: NIOS II from Altera, MicroBlaze form XilinxSoC integration of main system elements like microprocessor, timers, registers, memory controllers or communication modules in programmable device (FPGA)FPGA Field Programmable Gate Arrayregisters

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Processor communicationShared memory (SM)all processors have common address spaceprocessors can have own local memory (M)to communicate processors modify data in shared memoryMessage passingprocessors have separate address spacecommunication is realized by sending messagesprocessors are directly connected

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Resource sharingonly one of the processors should use the shared resource at the same timeto restrict access to shared resource should be used a semaphoreShared memory should be accessed only after successful acquiring of the semaphore

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Dual processor system designSystem tasks:control the time-to-digital converter in FPGAStatistical computation during time intervals measurementsMeasurement control via Internet connection

communicationprocessorcomputingprocessor

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Time-to-digital converter32 binary counters counting periods of 16-phase clock of the 400 MHz frequency (both edges of clock are active)equivalent of a single clock signal of 12.8 GHz frequencyprovides 78 ps resolution in a single stage interpolationmeasurement range 164 s can be easily extended

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System hardware overviewcommunicationprocessorcomputingprocessorFPGA device: Stratix II EP2S60 (Altera)

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Hardware implementationNios II Developement Kit Stratix II EditionFPGA device: Stratix II EP2S60 (Altera)Flash 16MBDDR SDRAM 32MBSSRAM 2MBUARTEthernetJTAGLEDsPush buttonsprototype connectors

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SoftwareTCP/IP stack implemantation from InterNiche NicheStackReal-time operating system (RTOS) for embedded devices C/OS-IIMultithreaded applicationCode optimized for statistical computationTime-to-digital converter software driversSingle threaded application

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Host PC applicationProgramming language: JAVAMeasurement control via Internet connection.Measurement result display.Measurement series histogram presentation.

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ConclusionFPGA resource utilizationSmall resource utilization 13% of Stratix II EPS2S60.System clock 100 MHzComputing power of one processor is reserved only for statistical computation.Measurement control via Internet connection.

Resource2uP System2uP System+ Timer CounterAvailable in Stratix IIALUT51206 36448 352Registers33924 22848352DSP blocks1616288Memory bits126464126 4642544192PLLs156

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Maciej GoaszewskiThank you for your attention

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Hello, my name is Maciej Goaszewski. Im a student of Electronic Faculty on Military University of Technology in Warsaw Poland. The subject of my work is Design and implementation of softcore dual processor system on single chip FPGA.