System Bus Noc

8/8/2019 System Bus Noc

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System Busses / Networks-on-Chip

EECE 579 - Advanced Topics in VLSI Design

Spring 2009

Brad Quinton


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Outline

1. Simple systems busses Overview

AMBAAPB

Advantages/Limitations

2. Complexsystems busses Overview AMBAAHB

Advantages/Limitations

3. Networks-on-Chip (NoC)

Overview AMBAAXI

Research Topics: Topology, Protocol, VLSIImplementation...

Review: A GenericArchitecture forOn-ChipPacket-SwitchedInterconnections


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Bluetooth PlatformSoC

ARM7TDMI

DAP I/F

RADIO

I/F

SPEECH

I/F

SHARED

MEMORY

CONTROLLER

LM C

BRIDGE

POW ER &

CLOCK

CONTROL

DM A

SM C

PLL

CLOCKS

SHARED

MEMORY

TI C

DECODER

ARBITER

AH B AP B

AD C

t xt ACI USBUARTUART

TIMERSPICGPIOW ATCH

DOG

ProcessorMemory

Controller

ApplicationSpecificLogic

Low-speedI/OandSupportLogic

SystemBus/Hardware

I/F


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SimpleSystemBusses


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SimpleSystemBusses

Theprimary goalofasimplesystem busistoallowsoftware (runningonaprocessor) tocommunicate

with otherhardware intheSoC

Therearemany differentimplementation ... buttheyareallvery similar


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EmbeddedProcessorI/O

RISC-basedembeddedprocessorscommunicatewith external hardwareusingtwosimpleinstructions:


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LoadOperation: Copiesawordofdata fromaspecificaddresstoalocalregister

StoreOperation: Copiesawordofdata fromalocal

register toaspecificaddress


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LoadOperation: Copiesawordofdata fromaspecificaddresstoalocalregister

StoreOperation: Copiesawordofdata fromalocal

register toaspecificaddress

Thesimplesystem busis justadirectextensionofthismodel


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Software

sets up the

register with

the address

and data ...


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Software

sets up the

register with

the address

and data ...

Blocks

decode

addresses

to see if

they are the

targets...


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Software

sets up the

register with

the address

and data ...

Blocks

decode

addresses

to see if

they are the

targets...

Datatransferred

between

register and

hardware


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AMBASpecification

AMBA:AdvancedMicrocontrollerBusArchitecture

Created by ARMtoenablestandardizedinterfacesto

theirembeddedprocessors

Actually threestandards:APB, AHB, andAXI

Ver y commonly used forcommercialIPcores


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AMBASpecification






Simple Bus


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AMBASpecification






Simple Bus Comple Bus


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AMBASpecification






NoCSimple Bus Comple Bus


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AMBAAPB:ReadOperation

QuickTime and aBMP decompressor

are needed to see this picture.


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Target Address


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Target Address

TransactionType


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Target Address

TransactionType

Address

Decode


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Target Address

TransactionType

Address

Decode

Optional (for

asynchronous

implementations

...)


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Target Address

TransactionType

Address

Decode

Optional (for

asynchronous

implementations

...)Read Data


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AMBAAPB: WriteOperation




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Common Signals

Between Read and

Write


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Write Data

Common Signals

Between Read and

Write


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RememberOurCaseStudy

- data width:16 bits

- address width: 16 bits

- read cycle time: 50 ns

- write cycle time: 50 ns

Simple generic processor interface:


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- data width:16 bits

- address width: 16 bits

- read cycle time: 50 ns

- write cycle time: 50 ns

Simple generic processor interface:

System bus

RememberOurCaseStudy


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SimpleBusAdvantages

Simpletoimplement

Easy tounderstand

Simpleprogrammingmodel

Easy toaddnew hardware blocks Minimal hardwarerequirements (mostofthesignals

areshared)


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SimpleBusLimitations

SingleMaster- limitsparallelism

Scalability - performancesuffersas busisloaded...

Singleoutstandingrequest- poorthroughputand

multi-threadingperformance bottleneck


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CaseStudy:SingleMaster

Imagineanewpartition:

APS Bit ErrorMonitorcommunicates

directly with Switch

Simple busdoesntwork...


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No ath






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No ath

Thiscanmakesoftwarethe bottleneckinthesystem....






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SingleMasterSummary

A busthatislimitedtoasinglemaster:

Makesinter-blockcommunicationinefficient

Limitsparallelism between hardwareandsoftware

Increasesrelianceoninterrupts

Createssoftwareperformance bottlenecks

Isnotcompatiblewith multipleprocessors


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Scalability


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Scalability

Blocks are functionally

easy to add, but....


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Scalability

Each new

block

increasesthe delay

on the

address

and data

Blocks are functionally

easy to add, but....


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SingleOutstandingRequest




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Processor is stalled waiting for response...


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Processor is stalled waiting for response...

best-case


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SingleOutstandingRequestSummary

Busseslimitedtoasingleoutstandingrequest:

Reducesoftwareperformancesincethesoftwaremuststallonthe firsttransaction

Arenotabletoachieve full busthroughputsincethedatabus isidleduringtheaddressphase


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ComplexSystemBusses


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ComplexSystemsBusses

Thecomplexsystem busisattemptstoaddresssomeoftheissueswith thesimple bus:

Multi-master

Pipelinedtransactions

Therearemany differentwaystogoaboutthis...


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AMBAAHB

AHBaddressesmany ofthelimitationsofAPB:

multi-master

multipleoutstandingtransactions (sortof...)

back-to-backtransactions

Unfortunately, thisaddssignificantcomplexity


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Bringonthecomplexity...


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CPU #1

CPU #2

IP lock

#1

IP lock

#1

IP lock

#2

IP lock

#3

IP lock

#4


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Request

CPU #1

CPU #2

IP lock

#1

IP lock

#1

IP lock

#2

IP lock

#3

IP lock

#4


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Request

GrantCPU #1

CPU #2

IP lock

#1

IP lock

#1

IP lock

#2

IP lock

#3

IP lock

#4


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Request

Grant

TransactionCPU #1

CPU #2

IP lock

#1

IP lock

#1

IP lock

#2

IP lock

#3

IP lock

#4


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BusArbitration

Whenmultiplemasterssharea bustheremust besomecentralresourcetomanagethe bus:anarbiter

Oncethereiscompetition forthe bus, itispossiblethatitisnotready when youneedit: backpressure

Backpressureaddscomplexity and hurtperformance


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Request/ GrantProtocol


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Before a transaction a

master makes a request

to the central arbiter


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Eventually the request is

granted


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granted

Then the

transaction

proceeds


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granted

Then the

transaction

proceeds

Performance Impact


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PipelinedTransactions

To helpimprove busefficiency thetransactionsonthe buscan bepipelined

Thisisreally asimpleimplementationofmultipleoutstandingtransactions

Theaddress foronetransactioncan bepresented

beforethedata fromtheprevioustransaction hasbeencompleted


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TransactionAStarts


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TransactionAStarts

TransactionBStarts


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TransactionAStarts

TransactionBStarts

TransactionA Completes


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TransactionAStarts

TransactionBStarts

TransactionA Completes

Notice backpressure


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Advantages

Relatively easy toaddnew blocks

Still hasthe familiarbusstructure

Low hardwarecost

Busarbitration solvesmany orderingproblems


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Disadvantages

Bussesthatrequirearbitration: mustroutesignalstothearbitrationlogicand back

mustfinda fairway tosharethe bus

slavesarenotalwaysavailable => backpressure

difficulttoprovideperformanceguarantees...

Stillpotentially a bandwidth bottleneck

Stilldoesntscalewellwhen blocksareadded

Multipleoutstandingtransactionsnot handledwell-

noorderinginformation


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Networks-on-Chip (NoCs)


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Networks-on-Chip

Itisclearthatevenwith significantdesigneffortthebus-styleinterconnectisnotgoingtosufficient forlargeSoCs:

thephysicalimplementation doesnotscale: bus fanout,loading, arbitrationdepth allreduceoperating frequency

theavailable bandwidth doesnotscale:thesingle bus

must beshared by allmastersandslaves


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Networks-on-Chip

Itisclearthatevenwith significantdesigneffortthebus-styleinterconnectisnotgoingtosufficient forlargeSoCs:

thephysicalimplementation doesnotscale: bus fanout,loading, arbitrationdepth allreduceoperating frequency

theavailable bandwidth doesnotscale:thesingle bus

must beshared by allmastersandslaves

Letsstartagain: Leverageresearch fromdatanetworking


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Whatdowewant?

TheSoCsofthe futurewill:

have 100sof hardware blocks,

have billionsoftransistors,

havemultipleprocessors,

havelargewire-to-gatedelay ratios,

handlelargeamountsof high-speeddata,

needtosupport plug-and-playIP blocks

Our NoCneedsto beready fortheseSoCs...


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TheIdeal Network

Whatwouldtheidealnetworklooklike?:

Lowareaoverhead

Simpleimplementation

High-speedoperation

Low-latency

High-bandwidth

Operateataconstant frequency evenwith additional

blocks Increaseavailable bandwidth as blocksareadded

Provideperformanceguarantees

Havea universalinterface


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TheIdeal Network

Whatwouldtheidealnetworklooklike?:

Lowareaoverhead

Simpleimplementation

High-speedoperation

Low-latency

High-bandwidth

Operateataconstant frequency evenwith additional

blocks Increaseavailable bandwidth as blocksareadded

Provideperformanceguarantees

Havea universalinterface

Thesearecompeting

requirements: Designa

networkthatisthe bestfit.


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Whatdoweneedtodecide?

NetworkInterface

NetworkProtocol/TransactionFormat

NetworkTopology VLSIImplementation


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NetworkInterface

Wewantournetworkto be plug-and-playsoindustry standardization iskey

However thestandard beuniversalenough toaddressmany differentneeds

AMBAAXIisanexampleofanattemptatthis


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AMBAAXI

ARMaddedtheAXIspecificationtoVersion3.0oftheAMBAstandard

Newapproach: definetheinterfaceandleavetheinterconnectuptothedesigners

Goodplansinceaspecific busimplementationisnolongerrequired

ItispossibletouseAXIto buildmany different NoCs


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AMBAAXI

Inter facedividedinto5channels:

WriteAddress

WriteData

WriteResponse

ReadAddress

ReadData/Response

Each channelisindependentandusetwo-way flowcontrol


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AMBAAXIRead Channels

C


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Independent

AMBA AXI R d Ch l


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Givemesomedata

Independent

AMBA AXI R d Ch l


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Givemesomedata

Here yougo

Independent

AMBA AXI R d Ch l


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Givemesomedata

Here yougo

Independent

channelssynchronizedwith ID # ortags

AMBA AXI W it Ch l


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AMBAAXI Write Channels

AMBA AXI W it Ch l


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Independent

Independent

AMBA AXI W it Ch l


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Imsendingdata. Pleasestoreit.

Independent

Independent

AMBA AXI W it Ch l


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Hereisthedata.

Independent

Independent

AMBA AXI W it Ch l


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Hereisthedata.

Ireceivedthatdatacorrectly.

Independent

Independent

AMBA AXI W it Ch l


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Hereisthedata.

Ireceivedthatdatacorrectly.

Independent

Independent

channelssynchronized

with ID # ortags

AMBA AXI Fl C t l


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AMBAAXIFlow-Control

Informationmovesonlywhen:

Source is Valid, and

DestinationisReady

Oneach channelthemasterorslavecanlimit

the flow

Ver y flexible

AMBA AXI Flo Control


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AMBAAXIFlow-Control

Informationmovesonlywhen:

Source is Valid, and

DestinationisReady

Oneach channelthemasterorslavecanlimit

the flow

Ver y flexible

Transfer

AMBA AXI Flow Control


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AMBAAXIFlow-Control

Thisdefinitionofvery independent, fully flow-controlledchannelsisvery useful

However , thereisapotentialproblem:



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AMBAAXIFlow-Control


However , thereisapotentialproblem:DEADLOCK



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AMBAAXIFlow-Control


However , thereisapotentialproblem:DEADLOCK

Onawritetransactionthemastermustnotwait forAWREADY beforeasserting WVALID

AMBA AXI Read


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AMBAAXIRead

AMBA AXI Read


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AMBAAXIRead

ReadAddress Channel

ReadData Channel

AMBA AXI Write


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AMBAAXI Write

AMBA AXI Write


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AMBAAXI Write

WriteAddress Channel

WriteResponse Channel

Write

Data

Channel

A True Interface Specification


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ATrueInterfaceSpecification

Becauseofthechannelindependence andthetwo-way flow-control theinterfacedoesnotdictatethenetworkprotocol, transaction format, networktopology, orVLSIimplementation

For example: if youwantto buildapacket-basednetwork, youcan

backpressurethedatachannelwhile you buildthe

packet headerfromtheaddresschannelinformation, youcanusestore-and-forward, orcut-through,

etc.

Network Protocol / Transaction Format


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Therearemany choice fornetworkprotocolsandtransactions formats:

circuit-switched :planandprovisionaconnection before

communicationstarts

packet-switched :issuespacketswhich compete fornetworkresources

hybrids: scheduleconnectivity (dynamicorstatic)

Network Protocol / Transaction Format


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Therearemany choice fornetworkprotocolsandtransactions formats:

circuit-switched :planandprovisionaconnection before

communicationstarts

packet-switched :issuespacketswhich compete fornetworkresources

hybrids: scheduleconnectivity (dynamicorstatic)

Thereisstilllotsofresearch here....

Network Topology


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NetworkTopology

Howshould yournetworkelements beinterconnected:

Fully Connected (N2): high areacost, high performance

Mesh: lowareacost, potentialpoorperformance

Hypercube:mediumarea, trafficdependentperformance

Fat-tree:mediumarea, trafficdependentperformance

Torus:mediumarea, trafficdependentperformance

Network Topology


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NetworkTopology

There is lots of research here....

Network Topology - Caveat


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NetworkTopology - Caveat

There has beenalotofresearch ontopologies forNoCs,howeveritisimportanttorealizethattheperformanceofatopology is highly dependentonthetrafficpatterns!

TrafficpatternsinanSoCthat youaredesigning yourselfare NOTrandom, thereforemuch ofthetopology researchisnotapplicabletomostSoCs!

VLSI Implementation


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VLSIImplementation

Once you haveatopology thereisstillthematerofimplementingiton yourSoC

Therearemany considerations:

Clocking: Synchronous, Asynchronous

BufferInsertion: Trade-offpower, area, performance

RegisterInsertion/Pipelining: Trade-offclock frequency, area,

andlatency PacketBuffers:Trade-offarea, latency andthroughput

Again, lotsofresearch on-going...

Bluetooth Platform SoC


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Bluetooth Platform SoC

ARM7TDMI

DAP I/F

RADIO

I/F

SPEECH

I/F

SHARED

MEMORY

CONTROLLER

LM C

BRIDGE

POW ER &

CLOCK

CONTROL

DM A

SM C

PLL

CLOCKS

SHARED

MEMORY

TI C

DECODER

ARBITER

AH B AP B

AD C

t xt ACI USBUARTUARTTIMERSPICGPIOW ATCH

DOG

Processor

Memory

Controller

ApplicationSpecificLogic

Low-speedI/OandSupportLogic

SystemBus/Hardware

I/F

Research Paper


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Research Paper

Letslookat:

Guerrier, P.; Greiner, A., "A generic architecture for on-chip

packet-switched interconnections ," Design, Automation and

Test in Europe Conference and Exhibition 2000. Proceedings

, vol., no., pp.250-256, 2000

System Bus Noc

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