전자정보대학 김영석 1

FINFET

김 영 석

충북대학교 전자정보대학

2017.3.1

Email: kimys@cbu.ac.kr

Introduction

전자정보대학 김영석 2

현재 MOSFET의 문제점: Short channel Effect로 인해

Drain-Induced-Barrier-Lowering 심하다

Subthreshold Swing S 크다

해결방법:

SOI(Silicon on Insulator)

FINFET

Bulk nmos Silicon on insulator

FinFet

DIBL(Drain-Induced-Barrier-Lowering)

Channel Length 짧아지면 드레인 전압에 의해 소스-채널의 장벽이 낮아져서 전류가 증가함. 이는 MOSFET의 스위칭 ON/OFF 특성을 악화시킴. OFF시에 leakage 전류가 흐름을 의미함.

해결: FINFET와 같이 Double Gate를 사용하여 게이트에 의한 채널 컨트롤을 증가시켜서 DIBL 완화시킴

전자정보대학 김영석 3

Subthreshold Swing S Subthreshold 동작 시에 채널의 전압(즉, npn BJT의 베이스-에미터 전압)과 드레인 전류:

Subthreshold Swing S는 다음과 같이 정의됨

S는 작을수록 좋다. Short Channel MOSFET는 S가 크다.

해결: SOI, FINFET와 같이 기판을 줄여 Cd를 증가시킴(Cd=es/Xd)

전자정보대학 김영석 4

TGS VVDD

oxd

GSGS

dox

oxC

eII

CCVV

CC

CV

/

0

/1

1 ,

η

ηη

=

+==

+=

)/1()10ln(log

10

oxdT

D

GS

GSD

CCVI

V

VIS

+=∆∆

=

∆= 필요한데증가시키는배

Dealing with Short Channel Effects in Fully depleted Silicon on Insulator (SOI)

Use ultra-thin film (tsi is small) as the conducting body, depletion layer is confined in the film.( Xd<= tsi).

Eliminate the junction parasitic capacitors.

Cuff off the leakage current path from drain to substrate.

전자정보대학 김영석 5

FINFET 구조 SOI + Double Gate => FINFET

Effective channel length Leff = Lgate + 2×Lext

Effective channel width W = Tfin + 2×Hfin

전자정보대학 김영석 6

Source Drain

Gate

Source Drain

Gate

Source Drain

Gate

FINFET Process Flow

전자정보대학 김영석 7 7

“Easy in concept----Tough to build”

(a) SiN is deposited as a hard mask, SiO2 cap is used to relieve the stress. (b) Si fin is patterned (c) A thin sacrificial SiO2 is grown (d) The sacrificial oxide is stripped completely to remove etch damage (e) Gate oxide is grown (f) Poly-Si gate is formed

10 nm gate length, 12 nm fin width

FINFET Performance

전자정보대학 김영석 8

FINFET Performance

전자정보대학 김영석 9

전자정보대학 김영석 10

FinFet characteristics

Lg = 15nm

Lg = 30nm

Threshold Voltage = 0.196 V

Subthreshold Slope = 72 mV/decade

Off Current = 70 ηA/µm

DIBL = 64.67 mV/V

Some values:

FINFET I-V

Square law?

One way is using nth power law to computer the FinFet current.

전자정보대학 김영석 11

FINFET 장점

Having excellent control of short channel effects in submicron regime and making transistors still scalable. Due to this reason, the small- length transistor can have a larger intrinsic gain compared to the bulk counterpart.

Much Lower off-state current compared to bulk counterpart.

Promising matching behavior.

전자정보대학 김영석 12

FINFET Applications

Low power design in digital circuit, such as RAM, because of its low off-state current.

Power amplifier or other application in analog area which requires good linearity.

전자정보대학 김영석 13