NDP6030PL(-30A)
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June 1997 NDP6030PL / NDB6030PL P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features ________________________________________________________________________________ Absolute Maximum Ratings T C = 25°C unless otherwise noted Symbol Parameter NDP6030PL NDB6030PL Unit s V DSS Dr ain- Sour c e Voltage - 30 V V GSS Gate- Source Vol t age - Continuous ± 16 V I D Drai n Current - Conti nuous - 30 A - Pul sed - 90 P D Total Power Dissipation @ T C = 25 ° C 75 W Derate above 25° C 0.5 T J ,T STG Operating and St orage Temper ature Range -65 to 175 °C T L Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds 275 ° C T J ,T STG Operating and St orage Temper ature Range -65 to 175 ° C THERMAL CHARACTERISTICS R θJC Thermal Resist anc e, Juncti on- to- Cas e 2 ° C/W R θJA Thermal Resi st anc e, Juncti on- to- Ambi ent 62.5 ° C/W NDP6030PL Rev.B1 -30 A, -30 V. R DS(ON) = 0.042 Ω @ V GS = -4.5 V R DS(ON) = 0.025 Ω @ V GS = -10 V. Critical DC electrical parameters specified at elevated temperature. Rugged internal source-dra in diode can eliminate the need for an external Zener diode transient suppressor. High density cell design for extremely low R DS(ON) . 175° C maximum junction temperature rating. These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as DC/DC converters and high efficiency switching circuits where fast switching, low in-line power loss, and resistance to transients are needed. S D G ©1997 Fa irchild Semicondu ctor Corpora tion
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